Prosecution Insights
Last updated: October 02, 2026
Application No. 19/093,890

METHOD, DEVICE, AND SYSTEM FOR ADAPTING DISTANCE PROTECTION AGAINST REACTANCE EFFECT DUE TO REMOTE INFEED AND FAULT RESISTANCE

Non-Final OA §102§103§DP
Filed
Mar 28, 2025
Priority
Apr 11, 2022 — IN 202241021576 +2 more
Examiner
COMBER, KEVIN J
Art Unit
Tech Center
Assignee
Hitachi Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
719 granted / 870 resolved
+22.6% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
28 currently pending
Career history
882
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
57.4%
+17.4% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
13.2%
-26.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 870 resolved cases

Office Action

§102 §103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-18 are pending in this application. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 03/28/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 15, 16, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn U.S. Patent No. 6,661,630 (hereinafter “Ahn”). Regarding claim 1, Ahn teaches a method for controlling a distance protection system (refer to abstract and figure 3), the method comprising: receiving, measurements comprising current and/or voltage measurements at a first position along a transmission line for an electrical power system (refer to step S100)(fig.3); computing a first impedance from the received measurements (refer to step S150)(fig.3); determining a fault location from the computed first impedance and a first impedance boundary (refer to step S160)(fig.3); computing, responsive to the determined fault location, a second impedance (refer to step S190)(fig.3); re-determining the fault location from the computed second impedance and the first impedance boundary (refer to step S270)(fig.3); and controlling the distance protection system from the determined fault location or the re-determined fault location (refer to step S280)(fig.3). Regarding claim 15, Ahn teaches the method of claim 1, wherein the determining the fault location from the computed first impedance and the first impedance boundary comprises determining whether the computed first impedance is inside of the first impedance boundary (refer to step S200 and S270)(fig.3). Regarding claim 16, Ahn teaches a device (refer to abstract and figures 1-3) for controlling a distance protection system (refer to abstract and figures 1-3) comprising a distance protection device (i.e. distance relay 20, 22)(figs.1 and 2) located at a first position (refer to figs.1 and 2) along a transmission line (i.e. transmission line 40)(figs.1 and 2) for an electrical power system (refer to abstract and figures 1 and 2), the device comprising a processor (inherent)(refer to fig.3) being configured to: receive measurements comprising current and/or voltage measurements at a first position along a transmission line for an electrical power system (refer to step S100)(fig.3); compute a first impedance from the received measurements (refer to step S150)(fig.3); determine a fault location from the computed first impedance and a first impedance boundary (refer to step S160)(fig.3); compute, responsive to the determined fault location, a second impedance (refer to step S190)(fig.3); re-determine the fault location from the computed second impedance and the first impedance boundary (refer to step S270)(fig.3); and control the distance protection system from the determined fault location or the re-determined fault location (refer to step S280)(fig.3). Regarding claim 18, Ahn teaches an electrical power system (refer to Ahn abstract and figures 1 and 2) comprising a transmission line (i.e. transmission line 40)(figs.1 and 2) and the device of claim 16 (refer to the rejection of claim 16 above). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 2, 3, 6-14, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn as applied to claims 1 or 16 above, and further in view of Qi et al. U.S. Patent Application 2016/0352091 (hereinafter “Qi”). Regarding claim 2, Ahn teaches the method of claim 1; however, Ahn does not teach the method further comprising re-determining the fault location from the computed first impedance and a second impedance boundary. However, Qi teaches the method further comprising re-determining the fault location from the computed first impedance and a second impedance boundary (refer to [0021]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ahn to include the second impedance boundary of Qi to provide the advantage of applying the method to the entire system to better localize the faults and trip only the necessary breakers/relays and prevent nuisance trips. Regarding claim 3, Ahn and Qi teach the method of claim 2, wherein the second impedance boundary is computed from the measurements obtained before a fault at the fault location occurs (refer to Qi [0021] and [0037]). Regarding claim 6, Ahn and Qi teach the method of claim 2, wherein the second impedance boundary is computed from a line impedance of the transmission line (refer to Qi [0021] and [0037]). Regarding claim 7, Ahn and Qi teach the method of claim 2, wherein the first impedance boundary is indicative of a first physical distance being a distance between the first position and a second position along the transmission line (refer to Qi [0016] and fig.2)(refer also to Ahn S and R)(fig.1). Regarding claim 8, Ahn and Qi teach the method of claim 7, further comprising determining, when the computed first impedance is inside of the first impedance boundary, the fault location is inside of the first physical distance (refer to Ahn step S270)(fig.3)(refer also to Qi fig.3). Regarding claim 9, Ahn and Qi teach the method of claim 8, wherein the determining the fault location from the computed first impedance and the first impedance boundary comprises determining whether the computed first impedance is inside of the first impedance boundary (refer to Ahn step S270)(fig.3)(refer also to Qi [0021]). Regarding claim 10, Ahn and Qi teach the method of claim 7, wherein the re-determining the fault location from the computed first impedance and the second impedance boundary comprises determining whether the computed first impedance is inside of the second impedance boundary (refer to Qi [0021]). Regarding claim 11, Ahn and Qi teach the method of claim 10, further comprising determining, when the computed first impedance is outside of the second impedance boundary, the fault location is outside of the first physical distance (refer to Qi [0021] and fig.3)(refer also to Ahn step S270)(fig.3). Regarding claim 12, Ahn and Qi teach the method of claim 7, wherein the re-determining the fault location from the computed second impedance and the first impedance boundary comprises determining whether the computed second impedance is inside of the first impedance boundary (refer to Ahn steps S200 and S270)(fig.3). Regarding claim 13, Ahn and Qi teach the method of claim 12, further comprising determining, when the computed second impedance is inside of the first impedance boundary, the fault location is inside of the first physical distance (refer to Qi [0021] and fig.3)(refer also to Ahn step S270)(fig.3). Regarding claim 14, Ahn and Qi teach the method of claim 7, wherein the determining the fault location from the computed first impedance and the first impedance boundary comprises determining whether the computed first impedance is inside of the first impedance boundary (refer to Qi [0021] and fig.3)(refer also to Ahn step S270)(fig.3). Regarding claim 17, Ahn teaches the device of claim 16; however, Ahn does not teach wherein the processor is further configured to re-determine the fault location from the computed first impedance and a second impedance boundary, wherein the second impedance boundary is computed from at least one of the measurements obtained before a fault at the fault location occurs, at least one impedance of an equivalent model of a two-port equivalent across the transmission line, or a line impedance of the transmission line. However, Qi teaches wherein the processor is further configured to re-determine the fault location from the computed first impedance and a second impedance boundary (refer to Qi [0021] and [0037]), wherein the second impedance boundary is computed from at least one of the measurements obtained before a fault at the fault location occurs (refer to Qi [0021] and [0037]), at least one impedance of an equivalent model of a two-port equivalent across the transmission line, or a line impedance of the transmission line (refer to Qi [0021] and [0037]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ahn to include the second impedance boundary of Qi to provide the advantage of applying the method to the entire system to better localize the faults and trip only the necessary breakers/relays to prevent nuisance trips. Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn and Qi as applied to claim 2 above, and further in view of Paladhi et al. “Adaptive Zone-1 Setting Following Structural and Operational Changes in Power System” (hereinafter “Paladhi”). Regarding claim 4, Ahn and Qi teach the method of claim 2; however, they do not teach wherein the second impedance boundary is computed from at least one impedance of an equivalent model of a two-port equivalent across the transmission line. However, Paladhi teaches wherein the second impedance boundary is computed from at least one impedance of an equivalent model of a two-port equivalent across the transmission line (refer to fig.2 and III. Determination of Relay Setting Parameters sections A-C on page 562). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ahn and Qi to include the equivalent model of Paladhi to provide the advantage of using a well-known method of quickly estimating impedances within a distribution line using little processing power. Regarding claim 5, Ahn, Qi, and Paladhi teach the method of claim 4, wherein the equivalent model of the two-port equivalent across the transmission line is estimated and/or updated from the measurements obtained before a fault at the fault location occurs (refer to Paladhi fig.2 and III. Determination of Relay Setting Parameters sections A-C on page 562). Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,288,979 (hereinafter “’979”. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-18 of ‘979 contain all of the limitations of claims 1-18 of the instant application, respectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN J COMBER/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Mar 28, 2025
Application Filed
Sep 18, 2026
Non-Final Rejection mailed — §102, §103, §DP (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
94%
With Interview (+11.8%)
2y 4m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 870 resolved cases by this examiner. Grant probability derived from career allowance rate.

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