DETAILED ACTION
This office action is responsive to application 19/094,249 filed on March 28, 2025. Claims 1-20 are pending in the application and have been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed on March 28, 2025 was received and has been considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2017/0339359).
Consider claim 1, Kim teaches:
An image sensor (see figures 3 and 4A) comprising:
a pixel (i.e. a pixel within the pixel array 10, figure 3, paragraph 0063); and
a comparator circuit (see figure 4A) configured to generate a comparison signal based on a ramp signal (RAMP SIGNAL, Vramp, figure 4A) and based on a pixel signal (PIXEL SIGNAL OF COMPARISON COLUMN, VPIXEL_N, figure 4A) received from the pixel (see paragraphs 0063 and 0072),
wherein the comparator circuit (see figure 4A) includes:
a comparator (comparison block, 410) including a first input node configured to receive the ramp signal (RAMP SIGNAL, Vramp, see figure 4A) and the pixel signal (PIXEL SIGNAL OF COMPARISON COLUMN, VPIXEL_N, see figure 4A) and a second input node configured to receive a reference signal (e.g. PIXEL SIGNAL OF ADJACENT COLUMN, VPIXEL_N-1, see figure 4A, paragraphs 0063 and 0072),
a first capacitor (first capacitor, C1) connected to the first input node (see figure 4A, paragraph 0074), and
a second capacitor (third capacitor, C3) connected to the second input node (see figure 4A, paragraph 0074),
wherein a distance from the first capacitor (C1) to the comparator (410) is shorter than a distance from the second capacitor (C3) to the comparator (410) in a first direction in a layout in a plan view (see figure 4A).
Consider claim 18, Kim teaches:
An image sensor (see figures 3 and 4A) comprising:
a pixel array comprising a plurality of pixels (pixel array 10, figure 3, paragraph 0063); and
a comparator circuit structure (comparison unit, 40, figure 3) including a plurality of capacitor circuits electrically connected to the pixel array (As shown in figure 3, there is one comparator (41A) for each column of the pixel array, paragraph 0067.),
wherein the plurality of capacitor circuits include first and second capacitor circuits configured to receive first and second pixel signals, respectively, from the pixel array (i.e. a first capacitor circuit for a first column and a second capacitor circuit for a second column of the pixel array, see figures 3 and 4A),
wherein the first capacitor circuit (see figure 4A) includes
a first comparator circuit (comparison block, 410) configured to receive a ramp signal (RAMP SIGNAL, Vramp, figure 4A) and the first pixel signal (PIXEL SIGNAL OF COMPARISON COLUMN, VPIXEL_N, see figure 4A), via a first input node thereof (see figure 4A), and to receive a first reference signal via a second input node thereof (e.g. PIXEL SIGNAL OF ADJACENT COLUMN, VPIXEL_N-1, see figure 4A, paragraphs 0063 and 0072),
a first sampling capacitor (first capacitor, C1) connected to the first input node (see figure 4A, paragraph 0074), and
a second sampling capacitor (third capacitor, C3) connected to the second input node (see figure 4A, paragraph 0074),
wherein a distance from the first input node of the first comparator circuit (410) to the first sampling capacitor (C1) in a first direction in a layout in a plan view is shorter than a distance from the second input node of the first comparator circuit (410) to the second sampling capacitor (C3) in the first direction in the layout in the plan view (see figure 4A),
wherein the second capacitor circuit (see figure 4A) includes:
a second comparator circuit (comparison block, 410) configured to receive the ramp signal (RAMP SIGNAL, Vramp, figure 4A) and the second pixel signal (PIXEL SIGNAL OF COMPARISON COLUMN, VPIXEL_N, see figure 4A) via a third input node thereof, and to receive a second reference signal via a fourth input node thereof (e.g. PIXEL SIGNAL OF ADJACENT COLUMN, VPIXEL_N-1, see figure 4A, paragraphs 0063 and 0072),
a third sampling capacitor (first capacitor, C1) connected to the third input node (see figure 4A, paragraph 0074), and
a fourth sampling capacitor (third capacitor, C3) connected to the fourth input node (see figure 4A, paragraph 0074),
wherein a distance from the third input node of the second comparator circuit (410) to the third sampling capacitor (C1) in the first direction in the layout in the plan view is shorter than a distance from the fourth input node of the second comparator circuit (410) to the fourth sampling capacitor (C3) in the first direction in the layout in the plan view (see figure 4A).
Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2016/0028981).
Consider claim 11, Lee et al. teaches:
A semiconductor device (figures 2 and 6) comprising:
a pixel array structure comprising a plurality of pixels (APS block, 120, figure 2, paragraph 0036); and
a first capacitor structure (see figure 6) configured to generate a comparison signal based on a first signal (PSi) and based on a second signal (VSS) received from the pixels (see figure 6, paragraph 0084),
wherein the first capacitor structure includes
a comparator (amplifier, 133-I, paragraph 0084) configured to receive the first and second signals (PSi and VSS) via a first input node (see figure 6) and to receive a third signal (RAMP) different from the first and second signals (PSi and VSS) via a second input node (see figure 6, paragraph 0084),
a first sampling capacitor (C2) connected to the first input node (see figure 6, paragraph 0093),
a second sampling capacitor (C3) connected to the second input node (see figure 6, paragraph 0093),
a first capacitor (C1) connected to a first node between the first sampling capacitor (C2) and the first input node (see figure 6, paragraph 0093), and
a second capacitor (C4) connected to a second node between the second sampling capacitor (C3) and the second input node (see figure 6, paragraph 0093),
wherein a capacitance of the first capacitor is different from a capacitance of the second capacitor (The capacitances of the first capacitor (C1) and second capacitor (C4) may be different as long as they are within a margin of error, paragraph 0061.).
Consider claim 12, and as applied to claim 11 above, Lee et al. further teaches that the capacitance of the first capacitor is smaller than the capacitance of the second capacitor (The capacitances of the first capacitor (C1) and second capacitor (C4) may be different as long as they are within a margin of error, paragraph 0061. This would include cases where the capacitance of the first capacitor is smaller than the capacitance of the second capacitor).
Allowable Subject Matter
Claims 2-10, 13-17, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 2, the prior art of record does not teach nor reasonably suggest that a distance from the first input node to the first capacitor in the first direction in the layout in the plan view is shorter than a distance from the second input node to the second capacitor in the first direction in the layout in the plan view, in combination with the other elements recited in parent claim 1.
Consider claim 3, the prior art of record does not teach nor reasonably suggest that the comparator circuit is configured to output a comparison result of comparing a difference between the ramp signal and the pixel signal with the reference signal, in combination with the other elements recited in parent claim 1.
Consider claim 4, and as applied to claim 1 above, Kim further teaches that the first capacitor includes:
a (1_1)-st capacitor having a first end connected to the first input node and a second end configured to receive the ramp signal (i.e. capacitor C2, figure 4A); and
a (1_2)-nd capacitor having a first end connected to the first input node and a second end configured to receive the pixel signal (i.e. capacitor C1, figure 4A).
However, the prior art of record does not teach nor reasonably suggest that the second capacitor includes (2_1)-st and (2_2)-nd capacitors connected in parallel with each other, wherein each of the (2_1)-st and the (2_2)-nd capacitors has a first end connected to the second input node, and a second end configured to receive the reference signal, in combination with the other elements recited in claims 1 and 4.
Claims 5-7 contain allowable subject matter as depending from claim 4.
Consider claim 8, the prior art of record does not teach nor reasonably suggest that the comparator circuit further includes: a third capacitor having a first end connected to a first node between the first capacitor and the first input node, and a second end connected to a ground; and a fourth capacitor having a first end connected to a second node between the second capacitor and the second input node, and a second end connected to the ground, in combination with the other elements recited in parent claim 1.
Consider claim 9, the prior art of record does not teach nor reasonably suggest that the comparator circuit further includes: a fifth capacitor having a first end connected to the first input node, and a second end connected to a third node between the first input node and a first output node of the comparator circuit; and a sixth capacitor having a first end connected to the second input node, and a second end connected to a fourth node between the second input node and a second output node of the comparator circuit, in combination with the other elements recited in parent claim 1.
Claim 10 contains allowable subject matter as depending from claim 9.
Consider claim 13, the prior art of record does not teach nor reasonably suggest that the first sampling capacitor includes: a (1_1)-st sampling capacitor having a first end connected to the first input node and a second end configured to receive the first signal; and a (1_2)-nd sampling capacitor having a first end connected to the first input node and a second end configured to receive the second signal, wherein the second sampling capacitor includes (2_1)-st and (2_2)-nd sampling capacitors connected in parallel with each other, wherein a first end of each of the (2_1)-st and the (2_2)-nd sampling capacitors is connected to the second input node, and a second end of each thereof is configured to receive the third signal, in combination with the other elements recited in parent claim 11.
Consider claim 14, the prior art of record does not teach nor reasonably suggest a substrate; and a second capacitor structure disposed on the substate and including a gate insulating film and a gate electrode, wherein the first capacitor structure is disposed on the second capacitor structure, in combination with the other elements recited in parent claim 11.
Claim 15 contains allowable subject matter as depending from claim 14.
Consider claim 16, the prior art of record does not teach nor reasonably suggest a substrate; and a second capacitor structure disposed on the substate and including a gate insulating film and a gate electrode, wherein the first capacitor structure is disposed on the second capacitor structure, in combination with the other elements recited in parent claim 11.
Claim 17 contains allowable subject matter as depending from claim 16.
Consider claim 19, and as applied to claim 18 above, Kim further teaches that the first sampling capacitor includes:
a (1_1)-st sampling capacitor having a first end connected to the first input node and a second end configured to receive the ramp signal (i.e. capacitor C2, figure 4A); and
a (1_2)-nd sampling capacitor having a first end connected to the first input node and a second end configured to receive the first pixel signal (i.e. capacitor C1, figure 4A).
However, the prior art of record does not teach nor reasonably suggest that the second sampling capacitor includes (2_1)-st and (2_2)-nd sampling capacitors connected in parallel with each other, wherein a first end of each of the (2_1)-st and the (2_2)-nd sampling capacitors is connected to the second input node, and a second end of each thereof is configured to receive the first reference signal, in combination with the other elements recited in claims 18 and 19.
Consider claim 20, and as applied to claim 18 above, Kim further teaches that the first sampling capacitor includes:
a (3_1)-st sampling capacitor having a first end connected to the third input node and a second end configured to receive the ramp signal (i.e. capacitor C2, figure 4A); and
a (3_2)-nd sampling capacitor having a first end connected to the third input node and a second end configured to receive the second pixel signal (i.e. capacitor C1, figure 4A).
However, the prior art of record does not teach nor reasonably suggest that the fourth sampling capacitor includes (4_1)-st and (4_2)-nd sampling capacitors connected in parallel with each other, wherein a first end of each of the (4_1)-st and (4_2)-nd sampling capacitors is connected to the fourth input node, and a second end of each of the (4_1)-st and (4_2)-nd sampling capacitors is configured to receive the second reference signal, in combination with the other elements recited in claim 18 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamashita et al. (US 2023/0209227) teaches a comparator structure for an image sensor (see figure 5) having two inputs (Vsl, Vramp) connected to a first input node and a reference signal (REF) connected to a second input node, thereof.
Shi et al. (US 2023/0179886) teaches a comparator structure for an image sensor (figure 4) having two inputs (Vramp, Vsig) connected to a first input capacitor (352) and a reference signal connected to a second input capacitor (351).
Purcell et al. (US 2009/0237536) teaches a comparator structure (figure 2) having a comparator (42) with two input capacitors (C1, C2) connected to a first input node (24) thereof, and a reference signal (Vref) connected to a third capacitor (C4) of a second input thereof.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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