DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 13-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 13 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: High-Bandwidth Memory (HBM), comprising: at least one core die; an interface die with the at least one core die stacked thereon, the interface die including: a first functional circuit configured to process a first signal for a first operating mode of the HBM; a second functional circuit configured to process a second signal for a second operating mode of the HBM; a direct access (DA) pad communicatively coupled to both the first and second functional circuits and configured to communicate both the first and second signals to/from an external device; and a multi-purpose communication mechanism configured to selectively enable processing of (1) the first signal at the first circuit when the HBM is in the first operating mode and (2) the second signal at the second circuit when the memory device is in the second operating mode, and a combination of other limitations in the independent claims.
Independent claim 18 comprise similar allowable content as that of claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alzheimer et al. (PGPUB 20230072895), hereinafter as Alzheimer.
Regarding claim 1, Alzheimer teaches a System-in-Package (SiP) device, comprising: an interposer having (1) a set of laterally extending connections and (2) a vertically extending via (Fig 1, SiP with interposer with lateral connections and via);
at least one processor (Fig 1, 110) mounted on the interposer and connected to the laterally extending connections (Fig 1); a memory device mounted on the interposer and having:
a set of signal pads (Fig 1, pads connected with lateral connections) connected to the set of laterally extending connections and configured to facilitate communications with the at least one processor, at least one direct access (DA) pad (Fig 1, vertical via and pads) connected to the vertically extending via and configured to facilitate communication of a first signal and a second signal with an external device, wherein the first signal corresponds to a first operating mode for the memory device and the second signal corresponds to a second operating mode for the memory device, a first circuit configured to process the first signal for the first operating mode, a second circuit configured to process the second signal for the second operating mode, and a multi-purpose communication mechanism configured to selectively enable processing of (1) the first signal at the first circuit when the memory device is in the first operating mode and (2) the second signal at the second circuit when the memory device is in the second operating mode ([0024] native mode vs test mode using native uBumps, test mode use DA/P1500 uBumps, and it is inherent a circuit corresponding a mode of operation).
Regarding claim 2, Alzheimer teaches the memory device is a high bandwidth memory (HBM) having a set of core dies stacked on an interface die, wherein the interface die includes at least the set of signal pads, the at least one DA pad, and the multi-purpose communication mechanism (Fig 1).
Regarding claim 3, Alzheimer teaches the first operating mode is a testing mode for validating functional operations of the HBM; the first signal includes a test input, a test command, a test result, or a combination thereof; and the first circuit includes a self-test circuit (Fig 5).
Regarding claim 4, Alzheimer teaches the HBM further includes a probe pad communicatively coupled to the first circuit and configured to provide direct access to the self-test circuit for the testing mode that occurs before the HBM is mounted on the interposer ([0018] to test the memory before it is mounted on the interposer).
Regarding claim 5, Alzheimer teaches a package substrate having the interposer mounted thereon and configured to provide external communication interface for the SiP, the package substrate having a DA external bump opposite the interposer and communicatively coupled to the DA pad on the HBM, wherein the DA external bump is for facilitating the communication of the first signal during the testing mode and the second signal during the second mode (Fig 1).
Regarding claim 6, Alzheimer teaches the second operating mode is a deployed operation mode for providing functional operations that occur after testing and/or validating the HBM ([0018]).
Regarding claim 7, Alzheimer teaches the memory device includes:
a first interface including a receiver, a transmitter, or both (Fig 2, receiver and transmitter associated with Native uBump) configured to communicate the first signal to/from the first circuit, wherein the first interface is connected to the DA pad;
a second interface including a receiver, a transmitter, or both (Fig 2, receiver and transmitter associated with uBump 216 and 220) configured to communicate the second signal to/from the second circuit, wherein the second interface is connected within the memory device to the DA pad and the first interface (Fig 2);
a probe pad connected within the memory device to the first interface, the second interface, and the DA pad ([0030]); and
the multi-purpose communication mechanism is configured to enable or activate (1) the first interface, the first circuit, or both for the first mode and (2) the second interface, the second circuit, or both for the second mode ([0024]).
Regarding claim 8, Alzheimer teaches
the DA pad is a first DA pad (Fig 2, uBump 205);
the memory device includes:
a second DA pad (uBump 216/220);
a first interface including a receiver, a transmitter, or both (Fig 2, receiver and transmitter associated with Native uBump 205) configured to communicate the first signal to/from the first circuit, wherein the first interface is connected to the first DA pad;
a second interface including a receiver, a transmitter, or both (Fig 2, receiver and transmitter associated with Native uBump 216/220) configured to communicate the second signal to/from the second circuit, wherein the second interface is connected to the second DA pad;
a probe pad (Fig 1, 115) connected within the memory device to the first interface and the first DA pad;
the interposer includes a parallel connection for providing the first and second signals to both the first DA pad and the second DA pad (Fig 1); and
the multi-purpose communication mechanism is configured to enable or activate (1) the first interface, the first circuit, or both for the first mode and (2) the second interface, the second circuit, or both for the second mode ([0024]).
Regarding claim 9, Alzheimer teaches
a common interface including a receiver, a transmitter, or both configured to communicate the first and second signals to/from both the first and second circuit, wherein the common interface is connected to the DA pad; a probe pad connected within the memory device to the DA pad and the common interface; and the multi-purpose communication mechanism is configured to enable or activate (1) the first circuit for the first mode and (2) the second circuit for the second mode (Fig 2, interface circuit).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alzheimer, in view of Ariki (PGPUB 20090001950), hereinafter as Ariki.
Regarding claim 10, Alzheimer teaches a device as in rejection of claim 1,
But not expressly two control signals are complementary,
Ariki teaches selectively enable processing based on generating (1) a first selection signal for enabling the processing of the first signal and (2) a second selection signal for enabling the processing of the second signal, wherein the first and second selection signals are complementary (Fig 1 and [0022-23]).
Since Ariki and Alzheimer are both from the same field of semiconductor memory device, the purpose disclosed by Ariki would have been recognized in the pertinent art of Alzheimer.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the complementary control as Ariki into the device of Alzheimer for the purpose of implementing only a choosing operation between the two operations.
Regarding claim 11, Alzheimer teaches a first input control circuit located at or before the first circuit and configured to allow the first signal into the first circuit according to the first selection signal; and a second input control circuit located at or before the second circuit and configured to allow the second signal into the second circuit according to the second selection signal (rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70).
Regarding claim 12, it well known that the multi-purpose communication mechanism includes a switch configured to electrically couple the DA pad to (1) the first circuit for the first operating mode and (2) the second circuit for the second operating mode (the examiner is taking note that a switch before two ends is well known in the field).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
