DETAILED ACTION
Claims 1 – 20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 7, 11-14, 16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wagh et al (US 9,985,912; hereinafter referred to as Wagh).
As per claims 1 and 12:
Taking claim 1 as exemplary: Wagh discloses network device, comprising: a plurality of network interfaces; an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device (Wagh: Figure 6); a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device (Wagh: Column 2 lines 22 – 39); and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted by the network device, the buffering scheme being selected among a first buffering scheme having a first latency associated with buffering packet data in the memory device and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data in the memory device (Wagh: Column 9 lines 9 – 24, using different buffering schemes based on congestion).
As per claims 2 and 13:
Taking claim 2 as exemplary: Wagh discloses the memory controller is configured to select the first buffering scheme, having the first latency, for buffering the packet when the network interface via which the packet is to be transmitted by the network device is congested; and select the second buffering scheme, having the second latency smaller than the first latency, when the network interface via which the packet is to be transmitted by the network device is not congested (Wagh: Column 9 lines 9 – 24).
As per claims 5 and 16:
Taking claim 5 as exemplary: Wagh discloses the memory controller is configured to in response to selecting the first buffering scheme, i) store the packet data in a buffer of the memory device, ii) retrieve the packet data from the buffer in response to receiving a read request from an egress processor and iii) provide the packet retrieved from the memory device to the egress processor; and in response to selecting the second buffering scheme, i) place the packet data in an early forward queue and ii) transmit the packet data from the early forward queue to an egress processor, coupled to the network interface via which the packet is to be transmitted from the network device, without receiving a read request from the egress processor (Wagh: Claim 1, the first buffering scheme uses the shared memory banks, the second buffering scheme uses the bypass mechanism, interpreting the bypass mechanism as equivalent to the claimed early forward queue).
As per claims 7 and 18:
Taking claim 7 as exemplary: Wagh discloses the memory controller is configured to cause the packet data to be transmitted from the memory device to an egress processor from either i) the buffer of the memory device or ii) the early forward queue of the memory device via a shared interface between the memory device and the egress processor (Wagh: Claim 1, using the shared memory or using the bypass mechanism).
As per claim 11:
Wagh discloses the egress processor is one of a plurality of egress processors of the network device, wherein respective ones of the plurality of egress processors are coupled to respective subsets of network interfaces among the plurality of network interfaces; and the memory device includes a shared buffer configured to store packet data directed to the plurality of egress processors (Wagh: column 2 lines 15 – 21, multiple egress ports and shared memory).
As per claim 14:
Wagh discloses providing the packet data from the memory device to an egress processor coupled to the network interface via which the packet is to be transmitted by the network device; and transmitting the packet, including the packet data, via the network interface (Wagh: Column 9 lines 25 - 35).
Allowable Subject Matter
Claims 3-4, 6, 8-10, 15, 17 and 19 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, either alone or in combination, fail to teach each and every limitation of the claims listed above, when taken in combination with all independent and intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sindhu et al (US 2010/0061391) teaches congestion resolution schemes from memory buffers having insufficient size and latency. Pan et al (US 9,674,104) teaches the control of queuing latency to buffer traffic and control congestion levels. Kalkunte (US 2014/0169189) teaches the choosing of a path for forwarding packets based on a network congestion map. Lee et al (US 2022/0166698) teaches congestion control schemes to mitigate the effects of congested queues or buffers on packet latency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZACHARY K HUSON whose telephone number is (571)270-3430. The examiner can normally be reached Monday - Friday 7:00 - 3:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZACHARY K HUSON/Primary Examiner, Art Unit 2181
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