DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed on 11/6/2025 fails to comply with the provisions of 37 CFR 1.98(a)(4) because it lacks the appropriate size fee assertion. It has been placed in the application file, but the information referred to therein has not been considered as to the merits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-12 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the element “the other image” in ll. 2 from the bottom. However, nowhere in the instant claim and its parent claims 1 and 10 indicates that there are only two images being transmitted from the processor to the display driver circuitry. Therefore, “the other image” is not definite.
Claim 12 is rejected because it depends on claim 11.
Claim 20 recites the element “the other image” in ll. 7 and ll. 9. However, nowhere in the instant claim and its parent claims 13 indicates there are only two images being transmitted from the processor to the display driver circuitry. Therefore, “the other image” is not definite. Furthermore, claim 20 recites the element “the other control command” in last line. However, nowhere in the instant claim and its parent claims 13 indicates there are only two control commands. Therefore, “the control command” is not definite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2020/0066226) in view of Cha et al. (US 2015/0029201).
Regarding claim 1, Han teaches an electronic device (Abstract: “electronic device”; Fig. 1: electronic device 1) comprising:
at least one processor (Figs. 1-2: processor 101) comprising processing circuitry (Fig. 2: inherent processing circuitry in processor 101);
a display (Figs. 1-2: display driver Integrated Circuit (IC) 200 and display 300) including a display panel (Figs. 1-2: display 300; [0057]: “The display 300 may be implemented as a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED) display, or an active-matrix OLED (AMOLED) display”) and display driver circuitry (Figs. 1-2: display driver Integrated Circuit (IC) 200; [0050]-[0056]) that includes a graphic (Fig. 2: frame memory 204); and
an interface (Fig. 2: first interface 110 and second interface 120; [0048]-[0050]; [0052]-[0053]), comprising circuitry (Fig. 2: inherent circuitry of first interface 110 and second interface 120 making them function as specified in the prior art), connecting the at least one processor to the display driver circuitry (Fig. 2),
wherein the display driver circuitry is configured to:
obtain, from the at least one processor, a control command (Fig. 2: control command associated with mode switching signal HS received from the host 100 through the second interface 120; Fig. 4: step 414, control command associated with mode switching signal HS=1; [0053]: “the controller 203 may identify, based on the mode switching signal HS, whether the display mode is a command mode or a video mode”; [0067]: “the processor 101 sets the mode switching signal HS to a logic ‘1’ or a logic high level and transmits the mode switching signal HS to the display driver IC 200 through the second interface 120”) indicating to change (Fig. 4: step 414, a change of control command from previously set mode switching signal HS=0 to newly set mode switching signal HS=1 corresponding to a change from video mode to command mode) a second mode executing an image transmission from the at least one processor to the display driver circuitry based on a timing identified by the at least one processor (Figs. 2, 4-5: second mode interpreted as video mode with processing path PATH2, whereby the processor 101 may transmit the image data DATA to the display driver IC 200 in real time and does not pass through frame memory 204) to a first mode executing the image transmission based on a timing identified by the display driver circuitry (Figs. 2, 4-5: first mode interpreted as command mode with processing path PATH1 for displaying a still iamge, whereby the processor 101 may transmit the image data DATA to the display driver IC 200 passing through the frame memory 204 not in real time);
store an image (Fig. 4: still image in step 413 that is displayed in real time in the video mode is the same as still image in step 416, which is stored in frame memory of processing path PATH1 in step 417 in view of Fig. 2; Figs. 2, 4-5 and [0069], [0071]: “During a high-level period (504 of FIG. 5) of the TE control signal TE after transmitting the mode switching signal HS, the host 100 transmits the image data DATA including still image data to the display driver IC 200 at step 416”, “After the high-level period 504 of the TE control signal TE, the display driver IC 200 may immediately transmit the image data DATA of a still image, received from the host 100 during the high-level period 504 of the TE control signal TE, to the display 300 through the command mode processing path PATH1 at step 417”; Examiner’s Note: in view of Fig. 2, command mode processing path PATH1 includes storing still image to frame memory 204) received via the interface (Fig. 2: first interface 110 employed for receiving image DATA) from the at least one processor in accordance with the image transmission executed based on the second mode
display, on the display panel, the image received via the interface from the at least one processor in accordance with the image transmission executed based on the second mode (Fig. 4: still image in step 413 is displayed in real time according to processing path PATH2, i.e., in the same manner as other moving images in video mode); and
in response to storing the image, change, based on the control command, the second mode to the first mode (Fig. 4: steps 417-418).
Han does not further expressly teach the frame memory is a graphic random access memory (GRAM). Instead, Han teaches in [0055] that “the frame memory 204 may be implemented as a graphic memory”.
However, it is common in the related art implementing a graphic memory as a graphic random access memory (GRAM).
Cha, for instance, teaches in Fig. 3 a frame memory implemented as a graphic random access memory (GRAM).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to modify the technique of Han with the technique of Cha having the frame memory 204 in Han’s technique implemented as a graphic random access memory (GRAM) to take advantage of the inherent advantage of GRAM technology, i.e., allowing recording information in a GRAM while reading the data in the GRAM to be displayed on a display.
Regarding claim 2, Han further teaches the electronic device of claim 1, wherein the display driver circuitry is configured to:
based on a refresh rate for the second mode, display, on the display panel, the image (Figs. 2 and 4-5: frame rate necessarily used in video mode with processing path PATH2, which is controlled by timing controller 205).
Regarding claim 3, Han further teaches the electronic device of claim 1, wherein the display driver circuitry is configured to:
in response to the changing from the second mode to the first mode, display again, on the display panel, the image by scanning the image in the GRAM based on a refresh rate for the first mode ([0055]: “In an example, the timing controller 205 may read data from the frame memory 204 during a high-level period of a frame scan signal Frame_Scan”; [0061]: “While the still image is not updated, the host 100 does not additionally transmit a still image to the display driver IC 200, and the display driver IC 200 may periodically read the output image data DDATA, prestored in a frame memory 204, and may transmit the output image data DDATA to the display 300”; Examiner’s Note: Frame_Scan signal is associated with a refresh rate, i.e., periodical reading of the output image data DDATA, of Command Mode being implemented).
Regarding claim 4, Han further teaches the electronic device of claim 1, wherein the display driver circuitry is configured to:
identify the refresh rate for the first mode that is indicated by another control command ([0055]: “In an example, the timing controller 205 may read data from the frame memory 204 during a high-level period of a frame scan signal Frame_Scan”; Examiner’s Note: Frame_Scan signal is associated with a refresh rate of Command Mode being implemented)
Regarding claim 5, Han in view of Cha in this embodiment does not further teach the electronic device of claim 1, wherein the display driver circuitry is configured to:
in response to the changing from the second mode to the first mode, refrain from processing another image received via the interface from the at least one processor in accordance with the image transmission executed based on the second mode in at least a portion of a time interval displaying again the image on the display panel.
In the same field of endeavor, Cha additionally teaches in Fig. 5:
in response to the changing from the second mode to the first mode, refrain from processing another image (Figs. 3 and 5; [0134]) received via the interface from the at least one processor in accordance with the image transmission executed based on the second mode in at least a portion of a time interval (Fig. 5: time interval between last pulse LP of the vertical synchronization signal Vsync and a first pulse FP of the internal vertical synchronization signal IVsync) displaying again the image on the display panel.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to further combine Cha’s additional teaching to Han’s technique in view of Cha to provide a smooth transition between the mode change.
Regarding claim 6, Han further teaches the electronic device of claim 3, wherein the display driver circuitry is configured to:
in response to the changing from the second mode to the first mode, provide, based on the refresh rate for the first mode, to the at least one processor, a signal ([0056]: “The timing controller 205 may generate a Tearing Effect (TE) control signal TE, and may transmit the generated TE control signal TE to the host 100. The processor 101 of the host 100 may monitor the TE control signal TE, and may control the transmission timing of the image data DATA based on the result of monitoring”) indicating a timing of the image transmission to be executed based on the first mode (Examiner’s Note control signal TE is monitored in a mode switching to indicate a timing for the image transmission to be executed based on the next mode).
Regarding claim 7, Han further teaches the electronic device of claim 1, further comprising:
memory comprising one or more storage media storing instructions ([0075]: “The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM)”) to, when executed by the at least one processor individually or collectively, cause the electronic device to:
in the second mode, execute periodic transmissions of a pulse signal (Fig. 5: periodic transmissions of a pulse signal for data transmission in time interval 503) to the display driver circuitry to synchronize at least one time interval (Fig. 5: time interval 503) in the display driver circuitry used for a displaying on the display panel with at least one time interval (Fig. 5: time interval 503) in the at least one processor used for the displaying on the display panel; and
after providing, to the display driver circuitry, the control command, cease the periodic transmissions (Fig. 5: in time period 505, the periodic transmission of pulses for data transmission from processor to display driving circuitry is ceased).
Regarding claim 8, Han further teaches the electronic device of claim 7, wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:
before changing a mode of the display driver circuitry from the second mode to the first mode, cease the periodic transmissions (Fig. 5: in later portion of time interval 504 with TE control signal TE at high-level, periodic transmissions of pulses for data transmission from processor to display driving circuitry is ceased).
Regarding claim 9, Han further teaches the electronic device of claim 1, further comprising:
another interface (Fig. 1: interface for transmitting the generated TE control signal TE by diplay driver IC 200 to the host 10) comprising circuitry, connecting the at least one processor to the display driver circuitry,
wherein the display driver circuitry is further configured to:
based on the control command, change a signal provided to the at least one processor via the another interface from a second signal (Fig. 5: earing Effect control signal TE generated in time interval 503) indicating whether enabling the image transmission to be executed based on the second mode to a first signal (Fig. 5: tearing Effect control signal TE generated in time interval 503) indicating a timing of the image transmission to be executed based on the first mode.
Regarding claim 11, Han further teaches the electronic device of claim 10, wherein the display driver circuitry is further configured to:
change the first mode to the second mode at least by receiving, via the interface, from the at least one processor, the other image in accordance with the image transmission executed based on the second mode ([0065]: “From a time point at which the high-level period 502 of the TE control signal TE ends, that is, from the falling edge of the TE control signal TE, the display driver IC 200 may immediately transmit the image data DATA of a video image, received from the host 100 during the high-level period 502 of the TE control signal TE, to the display 300 through the video mode processing path PATH2 at step 411).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2020/0066226) in view of Cha et al. (US 2015/0029201), and further in view of Maruyama et al. (US Patent NO. 11,238,779).
Regarding claim 10, Han further teaches the electronic device of claim 1, further comprising:
memory ([0075]: “The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM)”) comprising one or more storage media storing instructions, wherein the display driver circuitry is further configured to:
in the first mode, obtain, from the at least one processor, another control command (Fig. 5: ode switching signal HS in time period 501) indicating to change the first mode to the second mode; and
in response to the another control command, provide, to the at least one processor, a signal (Fig. 5: tearing effect control signal TE in time interval 502) indicating a request of the image transmission executed based on the second mode, and
wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:
within a reference time (Fig. 5: time defined by the portion of time interval 502 with Frame-Scan signal remaining at a high level) being from a timing obtaining the signal from the display driver circuitry, execute periodic transmissions of a pulse signal (Fig. 5: periodic transmissions of a pulse signal in the portion of time interval 502 with Frame-Scan signal at a low level; [0064]: “During the high-level period 502 of the TE control signal TE, the display 300 maintains the display state of the still image data of a previous frame”) to the display driver circuitry to synchronize at least one time interval in the display driver circuitry used for a displaying on the display panel with at least one time interval in the at least one processor used for the displaying on the display panel.
Han in view of Cha does not further teach:
in response to the number of the periodic transmissions reaching a reference number transmit, via the interface, to the display driver circuitry, another image in accordance with the image transmission executed based on the second mode.
The differentiating limitation indicates a specific synchronization technique for image transmission mode switching from a still image display mode (i.e., command mode) using internal oscillation signal OSC to a video mode using the external sync input.
The synchronization technique is not in the related art, however.
Maruyama, for instance, teaches in Col. 11, ll. 33-58 “The switching from the internal horizontal sync signal Hsync_int to the external horizontal sync signal Hsync_ext may be based on a count of assertions of the internal horizontal sync signal Hsync_int during the latter part of the second period. In one implementation, the selector 33 may switch the resultant horizontal sync signal Hsync from the internal horizontal sync signal Hsync_int to the external horizontal sync signal Hsync_ext in response to the count of the assertions of the internal horizontal sync signal Hsync_int reaching a predetermined number during the latter part of the second period”.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to further modify the technique of Han in view of Cha with Maruyama’s technique to reduce flicker effect during the display mode switching and achieve reliable synchronization between the processor and the display driver circuitry.
Claims 13-14, 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2020/0066226) in view of Cha et al. (US 2015/0029201), and further in view of Maruyama et al. (US Patent NO. 11,238,779).
Regarding claim 13, Han teaches an electronic device (Abstract: “electronic device”; Fig. 1: electronic device 1) comprising:
at least one processor (Figs. 1-2: processor 101) comprising processing circuitry (Fig. 2: inherent processing circuitry in processor 101);
memory comprising one or more storage media storing instructions ([0075]: “The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM)”);
a display (Figs. 1-2: display driver Integrated Circuit (IC) 200 and display 300) including
display driver circuitry (Figs. 1-2: display driver Integrated Circuit (IC) 200; [0050]-[0056]) including a graphic (Fig. 2: frame memory 204), and
a display panel (Figs. 1-2: display 300; [0057]: “The display 300 may be implemented as a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED) display, or an active-matrix OLED (AMOLED) display”); and
an interface (Fig. 2: first interface 110 and second interface 120; [0048]-[0050]; [0052]-[0053]), comprising circuitry (Fig. 2: inherent circuitry of first interface 110 and second interface 120 making them function as specified in the prior art), connecting the at least one processor to the display driver circuitry (Fig. 2),
wherein the display driver circuitry is configured to:
obtain, from the at least one processor, a control command (Fig. 2: control command associated with mode switching signal HS received from the host 100 through the second interface 120; Fig. 4: step 408, control command associated with mode switching signal HS=0; [0053]: “the controller 203 may identify, based on the mode switching signal HS, whether the display mode is a command mode or a video mode”; [0062]: “When the host 100 desires to transmit moving image data to the display driver IC 200 at step 407, the processor 101 sets the mode switching signal HS to a logic ‘0’ or a logic low level and transmits the mode switching signal HS to the display driver IC 200 through the second interface 120 at step 40”) indicating to change (Fig. 4: step 408, a change of control command from previously set mode switching signal HS=1 to newly set mode switching signal HS=0 corresponding to a change from command mode to video mode) a first mode (Fig. 4: command mode set for processing path PATH1 403 and for transmitting output image data DDATA from the display driver IC 200 to the display 300; Fig. 5: common mode implemented in time interval 501) to a second mode (Fig. 4: video mode set for processing path PATH2 409 and for immediately transmitting the image data DDATA of a video image from processor to display panel; Fig. 5: video mode implemented in time interval 503), wherein the first mode executes an image transmission from the at least one processor to the display driver circuitry based on a timing identified by the display driver circuitry (Figs. 2, 4-5: first mode interpreted as command mode with processing path PATH1 for displaying a still iamge, whereby the processor 101 may transmit the image data DATA to the display driver IC 200 passing through the frame memory 204 not in real time), and wherein the second mode executes the image transmission based on a timing identified by the at least one processor (Figs. 2, 4-5: second mode interpreted as video mode with processing path PATH2, whereby the processor 101 may transmit the image data DATA to the display driver IC 200 in real time and does not pass through frame memory 204);
in response to the control command, provide, to the at least one processor, a signal (Fig. 5: tearing effect control signal TE in time interval 502) indicating a request for the image transmission executed based on the second mode, and
wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:
within a reference time (Fig. 5: reference time interpreted as length of time interval 502 with Frame-Scan signal remaining at a high level) from a timing of obtaining the signal (Fig. 5: timing of tearing effect control signal TE in time interval 502) from the display driver circuitry, execute periodic transmissions of a pulse signal (Fig. 5: periodic transmissions of a pulse signal for data transmission in time interval 502) to the display driver circuitry, to synchronize (Figs. 2 and 5: with video mode implemented with processing path PATH2, processor 101 may transmit the image data DATA to the display driver IC 200 in real time, which necessarily requires synchronize the processor and the display driver IC 200) at least one time interval (Fig. 5: time interval 503) within the at least one processor to be used for displaying on the display panel with at least one time interval (Fig. 5: time interval 503) within the display driver circuitry.
Han does not further expressly teach
1) the frame memory is a graphic random access memory (GRAM); and
2) in response to the number of the periodic transmissions reaching a reference number, transmit, to the display driver circuitry via the interface, an image in accordance with the image transmission executed based on the second mode.
As for differentiating limitation 1), Han teaches in [0055] that “the frame memory 204 may be implemented as a graphic memory”.
However, it is common in the related art implementing a graphic memory as a graphic random access memory (GRAM).
Cha, for instance, teaches in Fig. 3 a frame memory implemented as a graphic random access memory (GRAM).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to modify the technique of Han with the technique of Cha having the frame memory 204 in Han’s technique implemented as a graphic random access memory (GRAM) to take advantage of the inherent advantage of GRAM technology, i.e., allowing recording information in a GRAM while reading the data in the GRAM to be displayed on a display.
As for differentiating limitation 2), it indicates a specific synchronization technique for image transmission mode switching from a still image display mode (i.e., command mode) using internal oscillation signal OSC to a video mode using the external sync input.
The synchronization technique is not in the related art, however.
Maruyama, for instance, teaches in Col. 11, ll. 33-58 “The switching from the internal horizontal sync signal Hsync_int to the external horizontal sync signal Hsync_ext may be based on a count of assertions of the internal horizontal sync signal Hsync_int during the latter part of the second period. In one implementation, the selector 33 may switch the resultant horizontal sync signal Hsync from the internal horizontal sync signal Hsync_int to the external horizontal sync signal Hsync_ext in response to the count of the assertions of the internal horizontal sync signal Hsync_int reaching a predetermined number during the latter part of the second period”.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to further modify the technique of Han in view of Cha with Maruyama’s technique to reduce flicker effect during the display mode switching and achieve reliable synchronization between the processor and the display driver circuitry.
Regarding claim 14, Han further teaches the electronic device of claim 13, further comprising:
another interface (Fig. 1: interface for transmitting the generated TE control signal TE by display driver IC 200 to the host 10) comprising circuitry, connecting the at least one processor to the display driver circuitry,
wherein the display driver circuitry is further configured to:
in response to the image, change a signal provided to the at least one processor via the another interface from a first signal (Fig. 5: tearing Effect control signal TE remained the same, e.g., in time interval 501) indicating whether enabling the image transmission to be executed based on the first mode to a second signal (Fig. 5: tearing Effect control signal TE is changed, e.g., in time interval 502) indicating a timing of the image transmission to be executed based on the second mode.
Regarding claim 16, Han further teaches the electronic device of claim 13, wherein the display driver circuitry is configured to change the first mode to the second mode at least by receiving the image from the at least one processor via the interface (Fig. 4: step 407).
Regarding claim 19, Han further teaches the electronic device of claim 13, wherein the display driver circuitry is configured to receive, from the at least one processor, another control command (Fig. 5: control command from HOST providing refresh rate of image/DATA transmission from HOST to display driver circuitry) indicating a refresh rate for the second mode together with the control command.
Regarding claim 20, Han further teaches the electronic device of claim 13, wherein the display driver circuitry is configured to:
obtain, from the at least one processor, another control command (Fig. 2: control command associated with mode switching signal HS received from the host 100 through the second interface 120; Fig. 4: step 414, control command associated with mode switching signal HS=1; [0053]: “the controller 203 may identify, based on the mode switching signal HS, whether the display mode is a command mode or a video mode”; [0067]: “the processor 101 sets the mode switching signal HS to a logic ‘1’ or a logic high level and transmits the mode switching signal HS to the display driver IC 200 through the second interface 120”) indicating to change (Fig. 4: step 414, a change of control command from previously set mode switching signal HS=0 to newly set mode switching signal HS=1 corresponding to a change from video mode to command mode) the second mode to the first mode, within the second mode;
store, in the GRAM, another image (Fig. 4: still image in step 413 that is displayed in real time in the video mode is the same as still image in step 416, which is stored in frame memory of processing path PATH1 in step 417 in view of Fig. 2; Figs. 2, 4-5 and [0069], [0071]: “During a high-level period (504 of FIG. 5) of the TE control signal TE after transmitting the mode switching signal HS, the host 100 transmits the image data DATA including still image data to the display driver IC 200 at step 416”, “After the high-level period 504 of the TE control signal TE, the display driver IC 200 may immediately transmit the image data DATA of a still image, received from the host 100 during the high-level period 504 of the TE control signal TE, to the display 300 through the command mode processing path PATH1 at step 417”; Examiner’s Note: in view of Fig. 2, command mode processing path PATH1 includes storing still image to frame memory 204) received via the interface from the at least one processor in accordance with the image transmission executed based on the second mode;
display, on the display panel, the other image received via the interface from the at least one processor in accordance with the image transmission executed based on the second mode (Fig. 4: still image in step 413 is displayed in real time according to processing path PATH2, i.e., in the same manner as other moving images in video mode); and
in response to storing the other image, change the second mode to the first mode based on the other control command (Fig. 4: steps 417-418).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2020/0066226) in view of Cha et al. (US 2015/0029201) and Maruyama et al. (US Patent NO. 11,238,779), and further in view of Han et al. (US 2021/0065652, referred to as Han ’652).
Regarding claim 15, Han further teaches
wherein the display driver circuitry is configured to:
display, on the display panel, the image, at least by scanning the image received via the interface from the at least one processor in accordance with the image transmission executed based on the second mode (Fig. 4: steps 410-412; Fig. 5: video mode implemented time interval 503);
Han in view of Cha and Maruyama does not further teach:
wherein the second signal is in a first state indicating to enable the image transmission to be executed based on the second mode or a second state indicating to disable the image transmission to be executed based on the second mode, and
in response to completion of the scanning of the image, change a state of the second signal from the second state to the first state.
The differentiating limitations appear to indicate use of an enable signal to control image data transmission when the second mode is implemented. Use of the enable signal is not new in the related art, however.
Han ’652, for instance, teaches in Figs. 4-5 and [0080]-[0081], [0090]-[0091]:
wherein the second signal (i.e., data enable signal DE1 in Fig. 5) is in a first state (Fig. 5: data enable signal DE1 at high level) indicating to enable the image transmission to be executed based on the second mode or a second state (Fig. 5: data enable signal DE1 at low level) indicating to disable the image transmission to be executed based on the second mode, and
in response to completion of the scanning of the image, change a state of the second signal from the second state to the first state (Fig. 4: steps 416-418; Fig. 5: image scanning is implemented when data enable signal DE1 is at high level within a frame; [0081]: “the host 100 transmits the image data to the display driver IC 200 through the data lane DATA while the data enable signal DE1 having a high logic level is transmitted through the clock lane CLK”; [0090]-[0091]).
Before the effective filing date of the invention, it would have been obvious to further modify the technique of Han in view of Cha and Maruyama with the technique of Han ’652 to achieve reliable synchronization between the Host including the processor and the display driver circuitry.
Allowable Subject Matter
Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 17: the limitation “in response to identifying that the periodic transmissions are not executed within the reference time from the timing obtained from the display driver circuitry, defer changing the first mode to the second mode” is not disclosed as a whole in prior art.
Claim 18: “the reference number varies according to the refresh rate for the second mode” is not disclosed as a whole in prior art.
Claim 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
In claim 12, the limitation “in response to identifying that the periodic transmissions are not executed within the reference time from the timing obtained from the display driver circuitry, defer changing the first mode to the second mode” is not disclosed as a whole in prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2024/0112620 is related technique by the same Applicant of this instant application.
US 2022/0180841 is related technique by the same Applicant of this instant application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XUEMEI ZHENG/Primary Examiner, Art Unit 2629