DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5 and 7-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nishida et al. (US PUB 2020/0072903), hereinafter Nishida.
With respect to claim 1, Nishida discloses a semiconductor device (See [1] in figure 1 of Nishida), comprising: a logic circuit (See [14] in figure 1 of Nishida); a diagnostic circuit (See [13] in figure 1 of Nishida), configured so as to perform a diagnostic process of diagnosing whether the logic circuit is in a state capable of normal operation (See paragraph [0047] of Nishida) based on output data of the logic circuit (See paragraph [0047] of Nishida) when a test pattern is supplied to the logic circuit (See paragraph [0042] of Nishida), and wherein the diagnostic circuit executes a plurality of diagnostic processes with operating conditions of the logic circuit that differ from each other (See paragraph [0048] in view of paragraphs [0025], [0079] and [0080] of Nishida).
With respect to claim 2, Nishida The semiconductor device as claimed in claim 1, wherein the logic circuit has a sequential circuit configured to operate in synchronization with a clock signal (See paragraph [0032] of Nishida), the diagnostic processes comprise a first diagnostic process (See paragraphs [0079] and [0080] of Nishida), a second diagnostic process (See paragraphs [0079] and [0080] of Nishida), and a third diagnostic process (See paragraphs [0079] and [0080] of Nishida), and the diagnostic circuit causes drive voltages of the logic circuit to be different from one another and frequencies of the clock signal to be different from one another among a first diagnostic process to a third diagnostic process (See [132] in figure 1 of Nishida).
With respect to claim 5, Nishida discloses the semiconductor device as claimed in claim 1, wherein the logic circuit has a sequential circuit configured to operate in synchronization with a clock signal (See paragraph [0032] of Nishida), the diagnostic processes comprise a first diagnostic process (See paragraphs [0079] and [0080] of Nishida) and a second diagnostic process (See paragraphs [0079] and [0080] of Nishida), and the diagnostic circuit causes drive voltages of the logic circuit to be different from one another and frequencies of a clock signal (See [132] in figure 1 of Nishida in view of paragraph [0043] of Nishida) to be different from one another between a first diagnostic process and a second diagnostic process (See [132] in figure 1 of Nishida).
With respect to claim 7, Nishida discloses the semiconductor device as claimed in claim 1, wherein the diagnostic circuit causes drive voltages of the logic circuit to be different from one another among the diagnostic processes (See paragraph [0043] of Nishida).
With respect to claim 8, Nishida discloses the semiconductor device as claimed in claim 1, wherein the logic circuit has a sequential circuit configured to operate in synchronization with a clock signal (See paragraph [0032] of Nishida), and the diagnostic circuit causes frequencies of the clock signal to be different from one another among the diagnostic processes (See paragraph [0043] of Nishida).
With respect to claim 9, Nishida discloses the semiconductor device as claimed in claim 1, wherein the semiconductor device is a power supply control device configured to control an operation of a power supply device by using the logic circuit (See paragraph [0027] of Nishida), the power supply device has a regulator of a plurality of channels (See paragraph [0027] in view of paragraph [0073] of Nishida), and is configured to be able to execute power conversion that generates an output voltage from an input voltage for each channel (See paragraph [0027] in view of paragraphs [0073] and [0102] of Nishida), the diagnostic circuit derives first result data or second result data through the diagnostic processes (See paragraph [0029] of Nishida), and the semiconductor device starts the power conversion in each of the channels after the first result data is derived by the diagnostic circuit (See paragraph [0046] of Nishida), and stops the power conversion in each of the channels in a case where the second result data is derived by the diagnostic circuit (See paragraph [0104] of Nishida).
Allowable Subject Matter
Claims 3 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, the prior art of record neither shows nor suggests the combination of structural elements wherein, in the first diagnostic process, the drive voltage of the logic circuit is a reference voltage and the frequency of the clock signal is a reference frequency, in the second diagnostic process, the drive voltage of the logic circuit is lower than the reference voltage and the frequency of the clock signal is lower than the reference frequency, and in the third diagnostic process, the drive voltage of the logic circuit is higher than the reference voltage and the frequency of the clock signal is higher than the reference frequency.
Claim 4 depends from objected to claim 3 and is therefore also objected to.
With respect to claim 6, the prior art of record neither shows nor suggests the combination of structural elements wherein the drive voltage of the logic circuit in the second diagnostic process is higher than the drive voltage of the logic circuit in the first diagnostic process, and the frequency of the clock signal in the second diagnostic process is higher than the frequency of the clock signal in the first diagnostic process.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PUB 2004/0095081 discloses a power converter circuitry and method.
US PUB 2003/0094934 discloses a semiconductor integrated circuit device and method of design
of semiconductor integrated circuit device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TEMILADE S RHODES-VIVOUR whose telephone number is (571)270-5814. The examiner can normally be reached M-F (flex schedule).
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/TEMILADE S RHODES-VIVOUR/ Examiner, Art Unit 2858
/RAUL J RIOS RUSSO/ Examiner, Art Unit 2858
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