Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Loading aware engine in claim 1, 2, 9 is equivalent to on-die hardware as described in 0031
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-15, 16-20 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Mohammad [20210124404]
As to claim 1,
Mohammad [20210124404] teaches A power distribution network (PDN) for power control of a processing unit, comprising:
a loading aware engine, configured to receive a plurality of characteristic signals from the processing unit[0010: “learning the coefficients of a power-frequency model for each compute element for the present workload ” 0070: “machine-readable medium includes any tangible mechanism that provides (i.e., stores and/or transmits in digital form, e.g., data packets) information in a form accessible by a machine (i.e., a computing device), which may be included, e.g., in a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, whether … to download and run applications ”], and
determine a loading information of the processing unit according to the plurality of characteristic signals using a trained model, wherein the loading information is related to a dynamic power and/or a dynamic current [0021: “estimating power, for a compute element, based on a current power model; reading actual power consumption of the compute element; performing weighted regression based on a difference between the actual power consumption and the estimated power; modifying the current power model based on the weighted regression; and determining a target frequency based on the modified current power model ”];
a clock generator, configured to provide a clock signal with an operating frequency to the processing unit [0118: “one or more clock generator circuitries, generally referred to as clock generator 5516. Clock generator 5516 generates clock signals at appropriate frequency levels, which may be supplied to any appropriate components of device 5500 ” and 0041: “Power/performance related parameters may include but are not limited to domain power, platform power, voltage, voltage domain current, die current, load-line, temperature, utilization, clock frequency, processing efficiency, current/future workload information, and other parameters. ” ] and
a controller, coupled to the loading aware engine and the clock generator [0088: “a computer system or a SoC (System-on-Chip) with workload aware power limiting and multiple-input multiple-output control, in accordance with some embodiments It is pointed out that those elements of FIG. 5 having the same reference numbers (or names) as the elements of any other figure may operate or function in any manner similar to that described, but are not limited to such.”], and configured to control the clock generator based on the loading information [0014: “To compute the maximum frequency, the embodiments dynamically learn the coefficients of a power-frequency model for a given workload and select the maximum frequency that stays within an overall input power limit. ” and 118: “clock generator 5516 is illustrated to be supplying clock signals to processor 5504 of device 5500. In some embodiments, clock generator 5516 receives one or more Frequency Identification (FID) signals, and generates the clock signals at an appropriate frequency, based on the FID signals. ”].
As to claim 2,
Mohammad [20210124404] teaches . The PDN of claim 1, further comprising: a voltage regulator, coupled to the controller, and configured to provide a supply voltage to the processing unit [00113: “power measurement circuitries 5542 may measure power, current and/or voltage supplied by one or more voltage regulators 5514, power supplied to SoC 5501, power supplied to device 5500, power consumed by processor 5504 (or any other component) of device 5500, etc. ” Also see, 0051-0055].
As to claim 3,
Mohammad teaches the controller comprises: a current and power controller, coupled to the loading aware engine, and configured to compare the loading information and a corresponding threshold of at least one threshold; and a hardware-based voltage/frequency (V/F) controller, coupled to the current and power controller, the clock generator, and the voltage regulator, and configured to control the voltage regulator and the clock generator, wherein, upon the current and power controller determining that the loading information is higher than the corresponding threshold, the current and power controller sends a throttle request to the hardware-based V/F controller, and the hardware-based V/F controller sends a frequency request to the clock generator for decreasing the operating frequency provided to the processing unit [0085: “At the second phase change at t=10 s, the selected frequency is roughly the same for STREAM and SPGEMM. At the third phase change at t=15 s, both methods choose a lower frequency for DGEMM than they did for SPGEMM. This is because the switching capacitance and power consumption of DGEMM is higher and the power budget (i.e. 160 W in this case) is reached at a lower frequency. ” Also. See 0115]
As to claim 4,
Mohammad teaches upon the current and power controller determining that the loading information is no longer higher than the corresponding threshold, the current and power controller stops sending the throttle request to the hardware-based V/F controller, and the hardware-based V/F controller controls the clock generator for recovering the operating frequency provided to the processing unit based on a given operating performance point [0042: “term “supervisee” generally refers to a power controller, or power management, unit (a “p-unit”), which monitors and manages power and performance related parameters for one or more associated power domains, either alone or in cooperation with one or more other p-units and receives instructions from a supervisor to set power and/or performance parameters (e.g., supply voltage, operating frequency, maximum current, throttling threshold, etc.) for its associated power domain. In examples where a die has one p-unit, a supervisee (Svee) p-unit may also be referred to as a supervisee die. Note that a p-unit may serve either as a Svor, a Svee, or both a Svor/Svee p-unit ” and 0115: “A state machine moves from a non-linear all ON state (which brings the output voltage Vout back to a regulation window) to an open loop duty cycle which maintains the output voltage slightly higher than the required reference voltage Vref. After a certain period in this state of open loop at the commanded duty cycle, the state machine then ramps down the open loop duty cycle value until the output voltage is close to the Vref commanded”]
As to claim 5,
Mohammad teaches upon the current and power controller determining that the loading information is no longer higher than the corresponding threshold and is lower than a corresponding offset threshold lower than the corresponding threshold, the current and power controller stops sending the throttle request to the hardware-based V/F controller, and the hardware-based V/F controller controls the clock generator for recovering the operating frequency provided to the processing unit based on a given operating performance point [ 0135: “the clock generator 5516 can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor 5504 has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU 5510 and/or PMIC 5512 performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, PCU 5510 and/or PMIC 5512 determines the operating condition of each core of a processor and opportunistically adjusts frequency and/or power supply voltage of that core without the core clocking source (e.g., PLL of that core) losing lock when the PCU 5510 and/or PMIC 5512 determines that the core is operating below a target performance level. For example, if a core is drawing current from a power supply rail less than a total current allocated for that core or processor 5504, then PCU 5510 and/or PMIC 5512 can temporality increase the power draw for that core or processor 5504 (e.g., by increasing clock frequency and/or power supply voltage level) so that the core or processor 5504 can perform at higher performance level. ”. Also 0143].
As to claim 6,
Mohammad teaches in response to a decrease in the operating frequency provided to the processing unit, the hardware-based V/F controller further sends a voltage request to the voltage regulator for decreasing the supply voltage provided to the processing unit to accommodate the decrease in the operating frequency provided to the processing unit [0143: “In some embodiments, a variant of the design can be used to sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches. This allows the sensor to not be exposed to the power supply voltage. In some embodiments, the amplifier with capacitively coupled inputs in feedback is used to compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing ”].
As to claim 7,
Mohammad teaches the corresponding threshold is a corresponding PDN limit [0013: “solves the challenge of scaling such that power caps (e.g., limits) are rapidly enforced even in computers where the cap must be enforced among a large pool of heterogeneous compute elements. The computational complexity of the technique scales substantially linearly (or linearly) with the number of compute elements under control. ”].
As to claim 8,
Mohammad teaches the loading information comprises total power and/or total current, the total power/current is a sum of the dynamic power/current and a leakage power/current, the dynamic power/current is determined according to the plurality of characteristic signals using the trained model, and the leakage power/current is obtained according to voltages and temperatures of the processing unit [113: “ power measurement circuitries 5542, e.g., for measuring power consumed by one or more components of the device 5500. In an example, in addition to, or instead of, measuring power, the power measurement circuitries 5542 may measure voltage and/or current. In an example, the power measurement circuitries 5542 may be embedded, or coupled or attached to various components, whose power, voltage, and/or current consumption are to be measured and monitored. For example, power measurement circuitries 5542 may measure power, current and/or voltage supplied by one or more voltage regulators 5514, power supplied to SoC 5501, power supplied to device 5500, power consumed by processor 5504 (or any other component) of device 5500, etc.”].
As to claim 9,
Mohammad teaches this claim according to the reasoning set forth in claim 1 supra.
As to claim 10-15,
Mohammad teaches this claim according to the reasoning set forth in claim 3-8 supra.
As to claim 16,
Mohammad teaches this claim according to the reasoning set forth in claim 1 supra.
As to claim 17,
Mohammad teaches this claim according to the reasoning set forth in claim 3 supra.
As to claim 18,
Mohammad teaches this claim according to the reasoning set forth in claim 5 supra.
As to claim 19,
Mohammad teaches this claim according to the reasoning set forth in claim 6 supra.
As to claim 20,
Mohammad teaches this claim according to the reasoning set forth in claim 8 supra.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571) 270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KESHAB R PANDEY/Primary Examiner, Art Unit 2176
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