DETAILED ACTION
Claim Objections
Claim 1 is objected to because of the following informalities:
On line 14, the limitation “such that the first end of the voltage supply rail” should be --such that the second end of the voltage supply rail--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dhong et al. (U.S. Patent 5,212,616, hereafter Dhong) in view of Perisetty (U.S. Patent 7,355,437).
Claim 5: Dhong teaches a latchup detection system (Figure 1; Abstract) comprising:
a voltage regulator (16, 18);
a chip (14);
a voltage supply rail (rail comprising Vddi) having a first end electrically coupled to an output of the voltage regulator (via 18) and a second end electrically coupled to an input of the chip (to 14);
a voltage feedback circuit (wire connecting Vddi to 16) that electrically couples the second end of the voltage supply rail to an input of the voltage regulator (to input of 16), wherein:
the output of the voltage regulator has a regulator output voltage (V'ref), the regulator output voltage is lowered to a target supply voltage at the second end of the voltage supply rail (Vddi has a target voltage; column 4 lines 27-35), and the voltage regulator is configured to adjust the target supply voltage to maintain the target supply voltage (via 16, 18 and the feedback to 16); a latchup detector (Figure 1; Abstract) comprising:
a level shifter (20) comprising: a first level-shifter circuit (portion of 20 connected to A) having an input electrically coupled to an output of a voltage regulator (V'ref); and
a second level-shifter circuit (portion of 20 connected to B) having an input electrically coupled to an input of a chip (Vddi connected to the input of 14), the input of the chip having a target supply voltage (value of Vddi; column 4 lines 27-35), wherein a voltage supply rail (rail comprising Vddi) is electrically coupled to the output of the voltage regulator (via 18) and to the input of the chip (to 14).
Claim(s) 8-9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Waite (U.S. Patent 5,642,069) in view of Girani et al. (U.S. Patent 11,108,358, hereafter Girani).
Claims 8 and 11: Waite teaches a clock-loss detector circuit (Figure 2) comprising:
a clock edge detector (22) having an input electrically coupled to a clock signal (16 via 10), the clock edge detector configured to produce a pulse signal (68) in response to a rising edge and/or a falling edge of the clock signal (column 4 lines 58-60), the pulse signal having a high value for a first time period and a low value for a second time period, the second time period longer than the first time period (68; Figure 4).
Waite does not specifically teach the details of the clock loss detector including a reset transistor.
Girani teaches a clock loss detector (Figure 4A) comprising a reset transistor (411) electrically coupled to an output of the clock edge detector (CLK corresponding to 68 of Waite) and to ground (GND), the reset transistor electrically coupled to ground when the pulse signal has the high value (column 7 lines 1-3), the reset transistor electrically decoupled from ground when the pulse signal has the low value (column 7 lines 18-21);
an output line (input to 414) electrically coupled to the reset transistor, the output line having an output voltage (voltage to 414), the output voltage equal to zero when the reset transistor is electrically coupled to ground (column 7 lines 18-21);
a capacitor (413) electrically coupled to the output line;
a current source (412) electrically coupled to the capacitor; and
a voltage detector (414) electrically coupled to the output line to measure the output voltage (column 7 lines 22-30), wherein the voltage detector is configured to produce an output signal when the output voltage is higher than a predetermined value (column 7 lines 22-30 where the Schmitt-trigger has a threshold level).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the detector taught by Girani in the circuit of Waite to detect frequency deviation (column 7 lines 35-37).
It is noted that claim 11 recites the limitations of claim 8 in method form and is rejected on the grounds above.
Claim 9: The combined circuit further teaches that the output voltage increases while the reset transistor is electrically decoupled from ground (column 7 lines 18-21 of Girani).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Waite in view of Girani and further in view of Sugie (U.S. Patent 8,004,338).
Claim 10: Waite and Girani teach the limitations of claim 8 above. Waite and Girani do not specifically teach the current source comprises a resistor electrically coupled in series with a power supply.
Sugie teaches a voltage generation circuit (74; Figure 1) comprising a current source (84) comprising a resistor (column 10 lines 7-15) electrically coupled in series with a power supply (Vdd).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the resistor taught by Sugie as the current source taught by Waite and Girani as an art-recognized equivalent circuit.
Allowable Subject Matter
Claims 1-4, 6 and 7 would be allowed if the claim objections stated above are resolved.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1 and 6, the prior art does not fairly teach or suggest a first end of a voltage supply rail is electrically coupled to the output of the voltage regulator, such that the first end of the voltage supply rail has the regulator output voltage, and a second end of the voltage supply rail is electrically coupled to the input of the chip, such that the second end of the voltage supply rail has the target supply voltage, the voltage supply rail having a routing resistance configured to decrease the regulator output voltage to the target supply voltage in combination with the limitations of claims 1 and 6.
Claims 2-4 and 7 are allowed merely for being dependent on claims 1 and 6.
Response to Arguments
Applicant’s arguments, filed January 6, 2026 with respect to the double patenting rejection have been fully considered and are persuasive. The double patenting rejection has been withdrawn.
Applicant’s arguments with respect to claims 1 and 6 have been fully considered and are persuasive. The rejections of claims 1-4 and 6 have been withdrawn.
Applicant's arguments with respect to claims 5, 8 and 10 have been fully considered but they are not persuasive.
Regarding claim 5, Applicant asserts that Dhong does not teach a voltage supply rail having a first end electrically coupled to an output of the voltage regulator and a second end electrically coupled to an input of the chip. Examiner respectfully disagrees. Dhong teaches a voltage supply rail (rail comprising Vddi) having a first end electrically coupled to an output of the voltage regulator (16, 18 are connected to Vddi via 18) and a second end electrically coupled to an input of the chip (Vddi is coupled to 14).
Regarding claims 8 and 10, Applicant asserts that Waite does not teach a clock edge detector configured to produce a pulse signal in response to a rising edge and/or a falling edge of the clock signal. Examiner respectfully disagrees. Waite teaches a clock edge detector (22; Figure 2) configured to produce a pulse signal (68; shown in detail in Figure 4) in response to a rising edge and/or a falling edge of the clock signal (column 4 lines 58-60, where the pulse signals indicate whether or not the clock signal is present). Examiner notes that Applicant points to Figure 6 of Waite, and asserts that 68 is not produced in response to a rising/falling edge of a clock. Examiner respectfully disagrees. Waite shows in Figure 6 that 68 is generated based on 122 and 124, both of which depend on clock signal A.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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