DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the Continuation filed on 03/31/2025
This is a CON of 18/108,249 now a PAT 12,267,581
Application claims a DP date of Mar 31, 2022
Claims 1, 9 and 16 are independent
Claims 1-20 are pending
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,267,581 B2. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the following table.
1. Application: A system comprising: a temperature sensor; and
1. Patent 12,267,581 B2: A system comprising: a temperature sensor; and
a processing apparatus that is configured to: access a temperature measurement from the temperature sensor;
1. Patent 12,267,581 B2 : a processing apparatus that is configured to: access a temperature measurement from the temperature sensor;
responsive to the temperature measurement being below a threshold, set a clock frequency for a clock signal used by an integrated circuit to a first frequency; and
1. Patent 12,267,581 B2 : responsive to the temperature measurement being below a threshold, set a clock frequency for a clock signal used by an integrated circuit to a first frequency, wherein the integrated circuit includes multiple power domain;
execute boot code in the integrated circuit using the clock signal at the first frequency,
1. Patent 12,267,581 B2: execute boot code in the integrated circuit using the clock signal at the first frequency,
wherein the first frequency is lower than a second frequency that the integrated circuit is configured to use when executing the boot code at temperature measurements above the threshold.
1. Patent 12,267,581 B2: wherein the first frequency is lower than a second frequency that the integrated circuit is configured to use when executing the boot code at temperature measurement above the threshold.
2. Application: comprising: a battery configured to provide power to the processing apparatus, wherein the temperature sensor is integrated with the battery.
2. Patent 12,267,581 B2: a battery configured to provide power to the processing apparatus, wherein the temperature sensor is integrated with the battery.
3. Application: wherein the processing apparatus includes the integrated circuit and a microcontroller that is used to access the temperature measurement and set the clock frequency for the clock signal.
3. Patent 12,267,581 B2: wherein the processing apparatus includes the integrated circuit and a microcontroller that is used to access the temperature measurement and set the clock frequency for the clock signal.
4. Application: wherein the processing apparatus includes the integrated circuit and the integrated circuit is configured to access the temperature measurement and set the clock frequency for the clock signal during an early phase of a boot sequence for the integrated circuit.
4. Patent 12,267,581 B2: wherein the processing apparatus includes the integrated circuit and the integrated circuit is configured to access the temperature measurement and set the clock frequency for the clock signal during an early phase of a boot sequency for the integrated circuit
5. Application: wherein the integrated circuit includes multiple power domains, and the processing apparatus is configured to: select a subset of the power domains in the integrated circuit for use during a boot sequence based on one or more temperature measurements from the temperature sensor.
1. Patent 12,267,581 B2: wherein the integrated circuit includes multiple power domains; select a first non-empty subset of the power domain in the integrated circuit for activation based on one or more temperature sensor;
6. Application: wherein the processing apparatus is configured to activate clock gater based on one or more temperature measurements from the temperature sensor
5. Patent 12,267,581 B2: wherein the processing apparatus is configured to activate a clock gater based on one or more temperature measurements from the temperature sensor.
7. Application: wherein the processing apparatus is configured to: responsive to the temperature measurement being below the threshold, apply automatic voltage scaling to one or more power domains of the integrated circuit.
6. Patent 12,267,581 B2: wherein the processing apparatus is configured to: responsive to the temperature measurement being below the threshold, apply automatic voltage scaling to one or more power domains of the integrated circuit.
8. Application: wherein the processing apparatus is configured to: run the integrated circuit in an idle mode after completing execution of the boot code, wherein the idle mode includes instructions that cause components of the processing apparatus to dissipate heat;
7. Patent 12,267,581 B2: wherein the processing apparatus is configured to: run the integrated circuit in an idle mode after completing execution of the boot code, wherein the idle mode includes instructions that cause components of the processing apparatus to dissipate heat;
compare one or more temperature measurements from the temperature sensor to a threshold associated with a selected use case; and
7. Patent 12,267,581 B2: compare one or more temperature measurements from the temperature sensor to a threshold associated with a selected use case; and
responsive to the one or more temperature measurements exceeding the threshold associated with the selected use case, transition from the idle mode to an active mode that supports the selected use case.
7. Patent 12,267,581 B2: responsive to the one or more temperature measurements exceeding the threshold associated with the selected use case, transition from the idle mode to an active mode that supports the selected use case.
Claims 9-20 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,267,581 B2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-10, 13-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rajwan et al. (U.S. Patent Publication Number 2023/0031415 A1) in view of Bruno et al. (U.S. Patent Number 7,467,318 B2).
Regarding Claim 1, Rajwan discloses a system (Fig 1- Integrated Circuit 100) comprising:
a temperature sensor (Fig 1 – Temp sensor 111); and
a processing apparatus (Fig 1- First and second control loop 101, 121, Fig 3 – power management processor 301) that is configured to:
access a temperature measurement from the temperature sensor (Fig 3 – temperature sensing system 306);
responsive to the temperature measurement being below a threshold (Flow chart of Fig 8 – step 810 – temperature sensors detecting a temperature reaching a first temperature threshold), set a clock frequency for a clock signal used by an integrated circuit to a first frequency (Flow chart of Fig 8 – step 810 – reducing a frequency of a clock signal provided in response to one of the plurality of temperature sensors detecting a temperature reaching a first temp threshold); and
wherein the first frequency is lower than a second frequency that the integrated circuit is configured to use when executing the boot code at temperature measurements above the threshold (In ¶0022 Rajwan also discloses a second temperature threshold that is greater than the first temperature threshold. Further in ¶0038, Rajwan also teaches about clock control circuitry 324 which perform various frequency control functions. Some are based on signals received from power management. He also teaches about raising clock frequency, reducing clock frequency, dithering and inhibiting.).
Rajwan discloses all the limitations of the claim, but is silent about execute boot code in the integrated circuit using the clock signal at the first frequency.
Instead in a similar endeavor, Bruno discloses execute boot code in the integrated circuit using the clock signal at the first frequency (Bruno: In Col 10, lines 55-65, Bruno teaches about the frequency control data generator booting during initialization using the temperature data).
Rajwan and Pulver are combinable because both are related to temperature control in integrated circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to control the frequency during boot based on the temperature as taught by Bruno in the imaging module disclosed by Rajwan.
The suggestion/motivation for doing so would have been “to control adaptively varying frequency of a clock signal so as to ensure safe operation based on a circuit temperature” as disclosed by Bruno in the Abstract.
Therefore, it would have been obvious to combine Rajwan and Bruno to obtain the invention as specified in claim 1.
Regarding Claim 2, Rajwan in view of Bruno discloses comprising: a battery (Rajwan: Fig 11- power supply 1108 which represents a battery) configured to provide power to the processing apparatus, wherein the temperature sensor is integrated with the battery (Rajwan: In Fig 2 discloses supply voltage that is provided; Also see Fig 3 and ¶0036).
Regarding Claim 3, Rajwan in view of Bruno discloses wherein the processing apparatus includes the integrated circuit and a microcontroller (Rajwan: ¶0061 – controller 600 and PID CONTROLLER) that is used to access the temperature measurement (Rajwan: temp sensors 111) and set the clock frequency (Rajwan: Fig 1 and 2) for the clock signal (Rajwan: Fig 1 and 2 – integrated circuit 100, 200).
Regarding Claim 4, Rajwan in view of Bruno discloses herein the processing apparatus includes the integrated circuit and the integrated circuit is configured to access the temperature measurement and set the clock frequency for the clock signal during an early phase of a boot sequence for the integrated circuit (Bruno: In Col 10, lines 55-67, Bruno teaches that the frequency control data generator 410 is initially booted during initialization, the dynamic overclock frequency control data may read the initial temperature data corresponding to the junction temperature and then program the junction temperature threshold registers with appropriate dynamic threshold junction temperature data into the IC circuit 420).
Regarding Claim 6, Rajwan in view of Bruno discloses wherein the processing apparatus is configured to: activate a clock gater based on one or more temperature measurements from the temperature sensor (Rajwan: Rajwan, throughout his disclosure teaches about clock dithering – which has been interpreted as “clock gater”. Applicant has not defined “gater” in the claim or sufficiently discloses in the instant Specification. Since dithering involves in reduction of its frequency as disclosed by Rajwan, Examiner believes that Rajwan’s disclosure read on the limitations of Claim 6).
Regarding Claim 7, Rajwan in view of Bruno discloses wherein the processing apparatus is configured to: responsive to the temperature measurement being below the threshold, apply automatic voltage scaling to one or more power domains of the integrated circuit (Rajwan: In ¶0032, Rajwan discloses that in response to the temperature meeting or exceeding various threshold, the controller may generate clock signals and/or voltage control signals and further in ¶0037, he teaches that the voltage control circuitry 322 may perform various voltage control signals – like increasing or reducing voltage, or shut down in some instances, or placed in a sleep mode so as to conserve power).
Regarding Claim 8, Rajwan in view of Bruno discloses wherein the processing apparatus is configured to:
run the integrated circuit (Rajwan: Fig 1- Integrated Circuit 100; Fig 2- IC 200) in an idle mode (In ¶0021, Rajwan also discloses “switching” activity that can generate heat on an IC in response to detecting a voltage drop) after completing execution of the boot code (Bruno: In Col 10, lines 55-65, Bruno teaches about the frequency control data generator booting during initialization using the temperature data).,
wherein the idle mode includes instructions that cause components of the processing apparatus to dissipate heat (Rajwan: Rajwan’s disclosure of “increased workload” that could result in generation of heat – referred to as hotspots, such as execution of malicious code, as the claimed “idle mode”. In ¶0021, Rajwan also discloses “switching” activity that can generate heat on an IC in response to detecting a voltage drop);
compare one or more temperature measurements from the temperature sensor to a threshold associated with a selected use case (Rajwan: In ¶0021, Rajwan discloses a number of temperature sensors and control circuitry that compares reported temperatures to various thresholds and performs control actions based on these conditions); and
responsive to the one or more temperature measurements exceeding the threshold associated with the selected use case, transition from the idle mode to an active mode that supports the selected use case (Rajwan: Further in ¶0021, he discloses that when the first threshold is determined to be met or exceeded, the first control loop may cause a reduction of the frequency clock signal provided to circuity associated with a particular hotspot).
Regarding Claim 9, this claim is a methods claim that has limitation similar to claim 1. Claim 9 is rejected on the same grounds as Claim 1.
Regarding Claim 10, this claim is a methods claim that has limitation similar to claim 2. Claim 10 is rejected on the same grounds as Claim 2.
Regarding Claim 13, this claim is a methods claim that has limitation similar to claim 6. Claim 13 is rejected on the same grounds as Claim 6.
Regarding Claim 14, this claim is a methods claim that has limitation similar to claim 7. Claim 14 is rejected on the same grounds as Claim 7.
Regarding Claim 15, this claim is a methods claim that has limitation similar to claim 8. Claim 15 is rejected on the same grounds as Claim 8.
Regarding Claim 16, this claim is a methods claim that has limitation similar to claim 8. Claim 16 is rejected on the same grounds as Claim 8.
Regarding Claim 17, this claim is a methods claim that has limitation similar to claim 2. Claim 17 is rejected on the same grounds as Claim 2
Regarding Claim 20, this claim is a methods claim that has limitation similar to claim 7. Claim 20 is rejected on the same grounds as Claim 7.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Rajwan et al. (U.S. Patent Publication Number 2023/0031415 A1) in view of Bruno et al. (U.S. Patent Number 7,467,318 B2) as applied to claims 1, 9 and 16 above and further in view of Takayanagi et al. (U.S. Patent Number 10,001,800 B1).
Regarding Claim 5, Rajwan in view of Bruno discloses all limitations of Claim 1, but fails to clearly disclose wherein the integrated circuit includes multiple power domains, and the processing apparatus is configured to: select a subset of the power domains in the integrated circuit for use during a boot sequence based on one or more temperature measurements from the temperature sensor.
Instead in a similar endeavor, Tavakoli discloses wherein the integrated circuit (Fig 1- portable computing device PCD 100 mounted on the headset 199) includes multiple power domains (power management IC - PMIC), and the processing apparatus is configured to: select a subset of the power domains in the integrated circuit for use during a boot sequence (startup logic 250) based on one or more temperature measurements from the temperature sensor (In ¶0070, Tavakoli teaches that the CPU 110 may be coupled with on-ship thermal sensors 157A as well as off-chip thermal sensors 157C; In ¶0084, Tavakoli teaches that the startup logic 250 includes one or more executable instructions for selectively executing a select program for managing or controlling the core based on the temperature or power consumption levels with threshold temperature settings or power budget settings.).
Rajwan, Pulver and Tavakoli are combinable because both are related to temperature control in integrated circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the working of the startup logic as taught by Tavakoli in the imaging module disclosed by Rajwan in view of Bruno.
The suggestion/motivation for doing so would have been “reduce power consumption and mitigate thermal energy generation” as disclosed by Tavakoli in ¶0010.
Therefore, it would have been obvious to combine Rajwan, Bruno and Tavakoli to obtain the invention as specified in claim 5.
Regarding Claims 12 and 19, this claim is a methods claim that has limitation similar to claim 5. Claim 12 and 19 are rejected on the same grounds as Claim 5.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Rajwan et al. (U.S. Patent Publication Number 2023/0031415 A1) in view of Bruno et al. (U.S. Patent Number 7,467,318 B2) as applied to claims 9 and 16 above and further in view of Ginnela et al. (U.S. Patent Publication Number 2016/0116974 A1).
Regarding Claim 11, Rajwan in view of Bruno discloses all limitations of Claim 9, but fails to clearly disclose wherein the temperature sensor is inside a camera body with the integrated circuit.
Instead in a similar endeavor, Ginnela discloses wherein the temperature sensor is inside a camera body with the integrated circuit (Fig 1 of Ginnela’s teachings disclose a mobile device bootup system – where the mobile device 100 may refer to a smart phone which could be interpreted as a camera body.).
Rajwan, Pulver and Ginnela are combinable because both are related to temperature control in integrated circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the temperature sensors inside a camera body as taught by Ginnela in the imaging module disclosed by Rajwan in view of Bruno.
The suggestion/motivation for doing so would have been “segment a boot sequence and determining a first boot sequence since different environment factors such as heat could impact the boot sequence” as disclosed by Ginnela in ¶0072.
Therefore, it would have been obvious to combine Rajwan, Bruno and Ginnela to obtain the invention as specified in claim 11.
Regarding Claim 18, this claim is a methods claim that has limitation similar to claim 11. Claim 18 is rejected on the same grounds as Claim 11.
Reference Cited
The following prior art made of record but not relied upon is considered pertinent to applicant's disclosure.
Arabi et al. (U.S. Patent Publication Number 2000/0001634 A1) discloses methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.
Takayanagi et al. (U.S. Patent Number 10,001,800 B1) discloses techniques are disclosed relating to power management of an integrated circuit. In one embodiment, an integrated circuit includes a plurality of temperature sensors configured to measure a plurality of temperatures at different locations in the integrated circuit. The integrated circuit further includes a power management circuit configured to determine a set of guard bands based on a temperature difference determined using the plurality of temperatures. The power management circuit is configured to adjust, using the set of guard bands, a particular one of the plurality of temperatures, and to use the adjusted particular temperature to manage power consumption of the integrated circuit. In some embodiments, the power management circuit is configured to manage the power consumption by adjusting a voltage supplied to the integrated circuit, the adjusted voltage being based on the adjusted particular temperature.
Conclusion
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/PADMA HALIYUR/Primary Examiner, Art Unit 2639 July 15, 2026
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