DETAILED ACTION
This office action is in response to the application filed on 03/31/2025
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/17/2025 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 16-17 are objected to because of the following informalities: Claims 16-17 “the ADC” should be “the first ADC”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5 and 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pervaiz et al. US 2022/0393574.
Regarding Claim 1, Pervaiz teaches (Figures 1-7) a power management circuit (at fig. 1b) comprising: a switch matrix (at 111) configured to provide an output voltage based on an internal switch configuration (Vout); an output filter (Cout) coupled to the switch matrix; a sample and hold voltage sensor (s/h) coupled to the output filter and configured to take an analog voltage measurement (504a); a sample and hold current sensor coupled to the output filter and configured to derive an analog current measurement (504e); a first analog-to-digital converter (504e and 506a) coupled to the sample and hold voltage sensor (504a); a second ADC (504f and 506a) coupled to the sample and hold current sensor coupled to the sample and hold current sensor (504e); and a digital control and stabilization circuit (506c-d) coupled to the first ADC and the second ADC (see fig. 5) and configured to generate a signal (sent to 508a) that controls the switch matrix to produce a desired output voltage for a load (load receiving Vout). (For example: Par. 45-49 and 72-88)
Regarding Claim 2, Pervaiz teaches (Figures 1-7) further comprising a digital pulse width control circuit (506e) positioned between the switch matrix (see fig. 3) and the digital control and stabilization circuit (506c-d), the digital pulse width control circuit configured to transform the signal from the digital control and stabilization circuit to a pulse for the switch matrix (see fig. 6b-6c). (For example: Par. 94-98)
Regarding Claim 5, Pervaiz teaches (Figures 1-7)wherein the digital control and stabilization circuit (506c-d) is further configured to calculate a fast current feedback value (with 504f) based on the analog voltage measurement (par. 78, 82 and 86).
Regarding Claim 12, Pervaiz teaches (Figures 1-7) wherein the sample and hold voltage sensor (504) is configured to generate one sample per each clock cycle (with SHtriga). (For example: Par. 97 and 102)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Dwarakanath US 2005/0168205.
Regarding Claim 3, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach wherein the first ADC comprises a sparse ADC.
Dwarakanath teaches wherein the first ADC comprises a sparse ADC (140). (For example: Par. 35-36)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include wherein the first ADC comprises a sparse ADC as taught by Dwarakanath to faster control loops.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Prodic US 2011/0204859.
Regarding Claim 4, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach wherein the sample and hold current sensor is configured to measure current in an inductor in the output filter.
Prodic teaches (Figures 1-7) wherein the sample and hold (8) current sensor is configured to measure current in an inductor in the output filter (L). (For example: Par. 34-35 and 41-42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include wherein the sample and hold current sensor is configured to measure current in an inductor in the output filter, as taught by Prodic to ensure stability during transients.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Kernahan US 2004/0095266.
Regarding Claim 6, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach a calibration circuit configured to store an inductance value and a capacitor value associated with the output filter and provide the inductance value and the capacitor value to the digital control and stabilization circuit.
Kernahan teaches (Fig. 1-12) a calibration circuit (1205) configured to store an inductance value and a capacitor value (par. 499) associated with the output filter (see fig. 1) and provide the inductance value and the capacitor value to the digital control and stabilization circuit (see fig. 12). (For example: Par. 143-150, 153-154, 163 and 499)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include a calibration circuit configured to store an inductance value and a capacitor value associated with the output filter and provide the inductance value and the capacitor value to the digital control and stabilization circuit, as taught by Kernahan to provide different level precision voltages that are reliable.
Claim(s) 7-8 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Hyunh US 2021/0389354.
Regarding Claim 7-8, Pervaiz teaches (Figures 1-7) wherein the sample and hold voltage sensor (504a) is configured to sample a voltage for the analog voltage measurement (see fig. 5); wherein the sample and hold current sensor (504e) is configured to sample a measurement for the analog current measurement (see fig. 5). (For example: Par. 45-49 and 72-88)
Pervaiz does not teach the sample and hold sensor is configured to oversample
Hyunh teaches (Figures 1-5) the sample and hold sensor (510) is configured to oversample (par. 276).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include the sample and hold voltage sensor is configured to oversample, as taught by Hyun to improve quality of signal.
Regarding Claim 13, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach wherein the sample and hold voltage sensor is configured to generate multiple cycles per each clock cycle.
Hyunh teaches (Figures 1-5) wherein the sample and hold voltage sensor (510) is configured to generate multiple cycles per each clock cycle (par. 277).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include the sample and hold voltage sensor is configured to oversample, as taught by Hyun to improve quality of signal.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Hyunh US 2021/0389354 and further in view of Shen US 2018/0088183.
Regarding Claim 9, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach wherein the digital control and stabilization circuit is configured to estimate an inductance associated with the output filter from an inductor current slope.
Shen teaches wherein the digital control and stabilization circuit (1-3) is configured to estimate an inductance (of L) associated with the output filter (L and C) from an inductor current slope (par. 12).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include wherein the digital control and stabilization circuit is configured to estimate an inductance associated with the output filter from an inductor current slope, as taught by Shen to output a stable voltage that satisfies load requirements during the parameter identification process.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Melanson US 2008/0272946.
Regarding Claim 10, Pervaiz teaches (Figures 1-7) the digital pulse width control circuit (506e).
Pervaiz does not teach wherein the control circuit is configured to calculate a fractional cycle delay with a delta sigma circuit.
Melanson teaches (Figure 3 ) wherein the digital control circuit (302) is configured to calculate a fractional cycle delay (with 314) with a delta sigma circuit (with 302). (For example: Par. 35-39)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include wherein the control circuit is configured to calculate a fractional cycle delay with a delta sigma circuit, as taught by Melanson to avoid unwanted noise and stability problems.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Kosters US 2026/0280533.
Regarding Claim 11, Pervaiz teaches (Figures 1-7) the digital pulse width control circuit (506e).
Pervaiz does not teach wherein the control circuit is configured to calculate a fractional cycle delay with an edge interpolation circuit.
Kosters teaches (Figure 6) wherein the digital control circuit (at fig. 6) is configured to calculate a fractional cycle delay with an edge interpolation circuit (par. 20-21). (For example: Par. 46, 68 and 73)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include wherein the control circuit is configured to calculate a fractional cycle delay with an edge interpolation circuit, as taught by Kosters to reduce quantization noise in the system.
Claim(s) 14-15, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz in view of Levesque US 9900204.
Regarding Claims 14 and 20, Pervaiz teaches (Figures 1-7) the power management circuit (fig. 1b) comprising: a switch matrix (see fig. 3c) configured to provide an output voltage (Vout) based on an internal switch configuration; an output filter (Cout) coupled to the switch matrix; a sample and hold voltage sensor (504a) coupled to the output filter and configured to take an analog voltage measurement; a first analog-to-digital converter (504c and 506a) coupled to the sample and hold voltage sensor; a digital control and stabilization circuit (506c-d) coupled to the first ADC and configured to generate a control signal (from 506c or 506d); and a digital pulse width control circuit (506e) positioned between the switch matrix and the digital control and stabilization circuit (see figs. 6b-6c), the digital pulse width control circuit (506e) configured to transform the control signal from the digital control and stabilization circuit (from 506c-506d) to a pulse for the switch matrix (sent to 508a). (For example: Par. 45-49 and 72-88)
Pervaiz does not teach wherein the first ADC comprises a sparse ADC.
Levesque teaches (Figures ) a communication device (fig. 5) comprising: a transceiver (34 and 30) comprising a power amplifier (30) and a power management circuit (28 and 32) coupled to the power amplifier. (For example: Par. 206-209)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include a communication device comprising: a transceiver comprising a power amplifier and a power management circuit coupled to the power amplifier, as taught by Levesque to enable operation for providing power to a communication device.
Regarding Claim 15, Pervaiz teaches (Figures 1-7) wherein the digital control and stabilization circuit is configured to receive inductor current and output voltage feedback together with output capacitance current feedback (sensing input sent to 105, see fig. 3c) from the output filter (Cout). (For example: Par. 45-49 and 72-88)
Regarding Claim 18, Pervaiz teaches (Figures 1-7)wherein the digital control and stabilization circuit (506c-d) is further configured to calculate a fast current feedback value (with 504f) based on the analog voltage measurement (par. 78, 82 and 86).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz and Levesque and further in view of Dwarakanath US 2005/0168205.
Regarding Claim 16, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach wherein the ADC comprises a sparse predictive ADC architecture.
Dwarakanath teaches wherein the ADC comprises a sparse predictive ADC architecture. (For example: Par. 35-36)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include w wherein the ADC comprises a sparse predictive ADC architecture, as taught by Dwarakanath to faster control loops.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz, Levesque and Dwarakanath and further in view of Prodic US 2011/0204859.
Regarding Claim 17, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach wherein the ADC comprises a flash low resolution ADC with small range.
Prodic teaches (Figures 1-7) wherein the ADC comprises a flash low resolution ADC with small range (1-1). (For example: Par. 36-37 and 49)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include wherein the ADC comprises a flash low resolution ADC with small range, as taught by Prodic to ensure stability during transients.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pervaiz and Levesque and further in view of Kernahan US 2004/0095266.
Regarding Claim 19, Pervaiz teaches (Figures 1-7) the apparatus.
Pervaiz does not teach a calibration circuit configured to store an inductance value and a capacitor value associated with the output filter and provide the inductance value and the capacitor value to the digital control and stabilization circuit.
Kernahan teaches (Fig. 1-12) a calibration circuit (1205) configured to store an inductance value and a capacitor value (par. 499) associated with the output filter (see fig. 1) and provide the inductance value and the capacitor value to the digital control and stabilization circuit (see fig. 12). (For example: Par. 143-150, 153-154, 163 and 499)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pervaiz to include a calibration circuit configured to store an inductance value and a capacitor value associated with the output filter and provide the inductance value and the capacitor value to the digital control and stabilization circuit, as taught by Kernahan to provide different level precision voltages that are reliable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
