DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/31/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: OFFSET COMPENSATION CIRCUIT COMPENSATING AN OFFSET OF GAMMA AMPLIFIER USING A TRIMMING METHOD
Claim Objections
Claim 20 is objected to because of the following informalities:
As per claim 20, the limitation “identifying whether the polarity of the offset changes as the offset is compensated while a plurality of transistors included in an offset trimming circuit of the offset compensating circuit are activated in an order of greatest compensation voltage” should be “identifying whether the polarity of the offset changes as the offset is compensated while a plurality of transistors included in an offset trimming circuit of the offset compensating circuit are activated in an order of a greatest compensation voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 12 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishimura (US 20080180427).
As per claim 1, Nishimura discloses an offset compensating circuit (Abstract) comprising:
an input stage circuit comprising a first input circuit (Fig. 5A, #MP1-MP2), a second input circuit (#MN1-MN2), a first multiplexer (#SW1) configured to activate one of the first input circuit (#MP1-MP2) and the second input circuit (#MN1-MN2), a second multiplexer (#SW2) configured to change a polarity of an offset of a gamma voltage generation circuit (#38), and an offset trimming circuit configured to compensate the offset ([0067]-[0068]; [0070]; [0114]-[0115]; where an offset trimming circuit is inherently present);
an amplification stage circuit comprising a first current mirror (#MP5-MP6), a second current mirror (#MN5-MN6) and a third multiplexer (#SW3) configured to change the polarity of the offset ([0068]; [0070]);
an output stage circuit (#MN8-MP8) configured to receive voltages generated from the first current mirror and the second current mirror ([0068]); and
a switch (#SW1) configured to control a path connected to the output stage circuit or the input stage circuit ([0070]; [0074]).
As per claims 7 and 18, Nishimura discloses the offset compensating circuit (display driving circuit) of claim 1 (claim 12), wherein the offset compensating circuit is (implemented with) a complementary metal-oxide-semiconductor (CMOS) circuit ([0068]),
wherein the first input circuit comprises a plurality of PMOS transistors ([0068]), and
wherein the second input circuit comprises a plurality of NMOS transistors ([0068]).
As per claim 12, Nishimura discloses a display driving circuit (Abstract) comprising:
a driving controller (Fig. 3, #2; [0051]);
a gamma voltage generation circuit that is configured to receive an input voltage that is output from the driving controller and output a gamma voltage, wherein the gamma voltage generation circuit comprises an offset compensating circuit ([0056]);
a source driver (#3) configured to receive the gamma voltage and output a data signal ([0054]; [0056]); and
a gate driver (#4) configured to output a gate signal ([0055]),
wherein the offset compensating circuit comprises:
an input stage circuit comprising a first input circuit (Fig. 5A, #MP1-MP2), a second input circuit (#MN1-MN2), a first multiplexer (#SW1) configured to activate one of the first input circuit (#MP1-MP2) and the second input circuit (#MN1-MN2), a second multiplexer (#SW2) configured to change a polarity of an offset of the gamma voltage generation circuit (#38), and an offset trimming circuit configured to compensate the offset ([0067]-[0068]; [0070]; [0114]-[0115]; where an offset trimming circuit is inherently present);
an amplification stage circuit comprising a first current mirror (#MP5-MP6), a second current mirror (#MN5-MN6) and a third multiplexer (#SW3) configured to change the polarity of the offset ([0068]; [0070]);
an output stage circuit (#MN8- MP8) configured to receive voltages generated from the first current mirror and the second current mirror ([0068]); and
a switch (#SW1) configured to control a path connected to the output stage circuit or the input stage circuit ([0070]; [0074]).
Allowable Subject Matter
Claims 2-6, 8-11, 13-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of an offset compensating circuit comprising an input stage circuit comprising a first input circuit, a second input circuit, a first multiplexer configured to activate one of the first input circuit and the second input circuit, a second multiplexer configured to change a polarity of an offset of a gamma voltage generation circuit, and an offset trimming circuit configured to compensate the offset does not teach or fairly suggest the offset trimming circuit comprises: a p-channel metal-oxide semiconductor (PMOS) trimming circuit comprising a plurality of pairs of PMOS transistors and switches configured to individually control whether the PMOS transistors are activated; and an n-channel metal-oxide semiconductor (NMOS) trimming circuit comprising a plurality of pairs of NMOS transistors and switches configured to individually control whether the NMOS transistors are activated, wherein the plurality of PMOS transistors included in the PMOS trimming circuit have different compensation voltages, and wherein the plurality of NMOS transistors included in the NMOS trimming circuit have different compensation voltages, wherein the first multiplexer comprises a first sub multiplexer and a second sub multiplexer, wherein the first sub multiplexer is connected to a gate terminal of a first PMOS transistor among the plurality of PMOS transistors that is connected to a power voltage, wherein the second sub multiplexer is connected to a gate terminal of a first NMOS transistor among the plurality of NMOS transistors that is connected to a ground voltage, wherein the first sub multiplexer is configured to control whether to supply a PMOS bias voltage or the power voltage to the gate terminal of the first PMOS transistor, wherein the second sub multiplexer is configured to control whether to supply a NMOS bias voltage or the ground voltage to the gate terminal of the first NMOS transistor, wherein the plurality of PMOS transistors are activated based on the first PMOS transistor being activated, and wherein the plurality of NMOS transistors are activated based on the first NMOS transistor being activated, wherein the offset compensating circuit is configured to receive an input voltage that is divided into frames, wherein the switch is configured to: control the path in order for the first input circuit and the second input circuit of the input stage circuit and the output stage circuit not to be connected to each other in a first time period of each of the frames; and control the path in order for the second input circuit of the input stage circuit and the output stage circuit to be connected to each other in a second time period of each of the frames.
Claim 20 is allowed.
The following is an examiner’s statement of reasons for allowance: The prior art of a method of operating a display driving circuit including a driving controller, a gamma voltage generation circuit including an offset compensating circuit, a source driver and a gate driver does not teach or fairly suggest controlling a second multiplexer and a third multiplexer included in the offset compensating circuit to control the polarity of the offset to be a predetermined first polarity; identifying whether the polarity of the offset changes as the offset is compensated while a plurality of transistors included in an offset trimming circuit of the offset compensating circuit are activated in an order of greatest compensation voltage; and generating a trimming code corresponding to a result of identifying whether the polarity of the offset changes for each of the plurality of transistors.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 20150222252) discloses on Figure 4 and paragraph 0075, “a channel amplifier 140_1 includes a differential input unit 142, an upper bias unit including a PMOS transistor MPB a lower bias unit including an NMOS transistor MNB, a load stage 144, and an output stage 145”. Kim discloses on paragraph 0079, “The output stage 145 is electrically connected to the load stage 144, and connects an output terminal of the load stage 144 to the supply voltage VDD or the ground voltage. The load stage 144 may include an upper current source 146 connected to the N-type differential input unit and a lower current source 147 connected to the P-type differential input unit. The output stage 145 may include a PMOS transistor MPO1 which connects an output node to the supply voltage and an NMOS transistor MNO1 which connects the output node to the ground voltage”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/Examiner, Art Unit 2627
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627