DETAILED ACTION
This Action is responsive to the Response to Restriction filed on 07/14/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claims 21-38 in the reply filed on 07/14/2026 is acknowledged.
Claim Status
Claims 21-38 are elected without traverse. Claims 39-40 are amended. Claim 41 is newly presented. Claims 21-41 are pending and have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/15/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 31-32, 34-37, and 41 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11 and 12 of U.S. Patent No. 12197754 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated by the claims of the reference patent. See the following table for analysis, whereby limitations in bold are common between applications, and limitations in italics correspond to additional limitations are not common between applications:
Instant application 19/095,520
US 12197754 B2
21. An apparatus, comprising:
a host system connected to a memory sub-system; and a processing device configured to:
determine a superblock size of a plurality of memory superblocks in the memory sub-system;
record, into a log buffer, a sequence of logical addresses associated with a stream of write requests; and
send, to the memory sub-system, the stream of write requests.
10. A computing system, comprising:
a host system connected to a memory sub-system, the host system comprising a processing device configured via instructions to:
query, during booting up of the host system, a superblock size in the memory sub-system;
place write requests into a plurality of streams; allocate a plurality of log buffers for the plurality of streams respectively;
record, into the log buffers, a plurality of sequences of logical addresses as in the plurality of streams respectively;
send, to the memory sub-system, the write requests in the plurality of streams,
causing the memory sub-system to store data of the write requests into separate sets of superblocks for the plurality of streams respectively; and trim a first stream among the plurality of streams by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a first log buffer for the first stream, causing the memory sub-system to free at least one superblock.
31. The apparatus of claim 21, wherein the processing device is further configured to maintain a head pointer that identifies a first location in the log buffer that stores a starting logical block address of the sequence of logical addresses.
11. The computing system of claim 10, further comprising:
maintaining, by the host system, a head pointer identifying a location in the first log buffer storing a first logical address used in a beginning of a segment of the first stream stored in the memory sub-system
and a tail pointer identifying a location in the first log buffer storing a second logical address used in an end of the first stream.
32. The apparatus of claim 31, wherein the processing device is further configured to maintain
a tail pointer that identifies a second location in the log buffer that stores a last logical block address of the sequence of logical addresses.
11. The computing system of claim 10, further comprising:
maintaining,
by the host system, a head pointer identifying a location in the first log buffer storing a first logical address used in a beginning of a segment of the first stream stored in the memory sub-system and
a tail pointer identifying a location in the first log buffer storing a second logical address used in an end of the first stream.
34. An apparatus, comprising:
a host system connected to a memory sub-system; and a processing device configured to:
place a plurality of write requests into a plurality of streams;
allocate one of a plurality of log buffers to each one of the plurality of streams; and record, into each one of the plurality of log buffers, a respective plurality of sequences of logical addresses.
10. A computing system, comprising:
a host system connected to a memory sub-system, the host system comprising a processing device configured via instructions to:
query, during booting up of the host system, a superblock size in the memory sub-system;
place write requests into a plurality of streams;
allocate a plurality of log buffers for the plurality of streams respectively;
record, into the log buffers, a plurality of sequences of logical addresses as in the plurality of streams respectively;
send, to the memory sub-system, the write requests in the plurality of streams,
causing the memory sub-system to store data of the write requests into separate sets of superblocks for the plurality of streams respectively; and trim a first stream among the plurality of streams by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a first log buffer for the first stream, causing the memory sub-system to free at least one superblock.
35. The apparatus of claim 34,
the processing device further configured to
determine a superblock size associated with superblocks of the memory sub-system.
10. A computing system, comprising:
a host system connected to a memory sub-system, the host system comprising a processing device configured via instructions to:
query, during booting up of the host system, a superblock size in the memory sub-system;
place write requests into a plurality of streams; allocate a plurality of log buffers for the plurality of streams respectively;
record, into the log buffers, a plurality of sequences of logical addresses as in the plurality of streams respectively; send, to the memory sub-system, the write requests in the plurality of streams, causing the memory sub-system to store data of the write requests into separate sets of superblocks for the plurality of streams respectively; and trim a first stream among the plurality of streams by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a first log buffer for the first stream, causing the memory sub-system to free at least one superblock.
36. The apparatus of claim 35,
wherein the processing device is further configured to
determine the superblock size during a boot up of the host system.
10. A computing system, comprising:
a host system connected to a memory sub-system, the host system comprising a processing device configured via instructions to:
query, during booting up of the host system, a superblock size in the memory sub-system;
place write requests into a plurality of streams; allocate a plurality of log buffers for the plurality of streams respectively;
record, into the log buffers, a plurality of sequences of logical addresses as in the plurality of streams respectively; send, to the memory sub-system, the write requests in the plurality of streams, causing the memory sub-system to store data of the write requests into separate sets of superblocks for the plurality of streams respectively; and trim a first stream among the plurality of streams by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a first log buffer for the first stream, causing the memory sub-system to free at least one superblock.
37. The apparatus of claim 34,
wherein the processing device is further configured to
send, to the memory sub-system, each of the plurality of streams,
wherein each of the plurality of streams causes the memory sub-system to store data associated with the plurality of write requests associated with the plurality of streams.
10. A computing system, comprising:
a host system connected to a memory sub-system, the host system comprising a processing device configured via instructions to:
query, during booting up of the host system, a superblock size in the memory sub-system;
place write requests into a plurality of streams; allocate a plurality of log buffers for the plurality of streams respectively;
record, into the log buffers, a plurality of sequences of logical addresses as in the plurality of streams respectively;
send, to the memory sub-system, the write requests in the plurality of streams,
causing the memory sub-system to store data of the write requests into separate sets of superblocks for the plurality of streams respectively;
and trim a first stream among the plurality of streams by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a first log buffer for the first stream, causing the memory sub-system to free at least one superblock.
41. An apparatus, comprising:
a memory and a processing device configured to:
place a plurality of write requests into a plurality of streams; and
allocate one of a plurality of log buffers to each one of the plurality of streams.
10. A computing system, comprising:
a host system connected to a memory sub-system, the host system comprising a processing device configured via instructions to:
query, during booting up of the host system, a superblock size in the memory sub-system; place write requests into a plurality of streams;
allocate a plurality of log buffers for the plurality of streams respectively;
record, into the log buffers, a plurality of sequences of logical addresses as in the plurality of streams respectively; send, to the memory sub-system, the write requests in the plurality of streams, causing the memory sub-system to store data of the write requests into separate sets of superblocks for the plurality of streams respectively; and trim a first stream among the plurality of streams by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a first log buffer for the first stream, causing the memory sub-system to free at least one superblock.
As shown in the analysis above, every limitation recited in Claims 21, 31-32, 34-37, and 41 is anticipated by Claims 10 and 11 of the reference patent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21, 25-27, 34-35, and 37-41 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanno (US 20210064290 A1)(hereafter referred to as Kanno ‘290).
Regarding Claim 21,
Kanno ‘290 anticipates the following limitations:
An apparatus (Fig. 1), comprising:
a host system (Host 2, Fig. 1) connected to a memory sub-system (SSD 3, Figs. 1 / 2); and a processing device (Controller 4, Fig. 2) configured to:
determine a superblock size of a plurality of memory superblocks in the memory sub-system; (“A write destination block may be one physical block or one superblock. The structure wherein each superblock includes only one physical block may be adopted. In this case, each superblock is equivalent to one physical block.” [0047] // “the write control unit 21 allocates a plurality of write destination blocks corresponding to a plurality of streams from a plurality of blocks of the NAND flash memory 5, and manages the allocated write destination blocks” [0062]) – Write control unit allocates superblocks, sized according to one physical NAND flash block, to a plurality of streams--
record (¶0121), into a log buffer (Command Queue 41-1, Fig. 9), a sequence of logical addresses (“an LBA of write data” [0119]) associated with a stream of write requests (“Each write command includes an LBA of write data, the length of write data, a stream ID, and a data pointer indicative of a location in the write buffer 51 in which write data is stored … Each write command including the stream ID #1 is stored in the command queue 41-1” [0119-121]) – Write commands associated with a particular stream #1 and including respective LBAs (i.e., “a sequence of logical addresses”) are recorded into a corresponding command queue 41-1 allocated to stream #1--; and
send (¶0125), to the memory sub-system, the stream of write requests. (“When the length of write data associated with a set of write commands belonging to a group corresponding to a stream reaches the minimum write size, the write control unit 21 transmits, to the DMAC 15, a transfer request to transfer write data having the minimum write size … the DMAC 15 performs a DMA transfer and thereby transfers the write data having the minimum write size, associated with the stream, from the write buffer 51 in the host memory to the internal buffer. Then, the write control unit 21 sends a program instruction to the NAND interface … to a write destination block in the NAND flash memory 5.” [0125] // Fig. 9) – Once an amount of write data corresponding to the minimum write size is reached for a respective stream, the write data associated with the stream written to NAND.
Regarding Claim 25,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 21, wherein each of the plurality of memory superblocks in the memory sub-system has a same size. (“In this case, each superblock is equivalent to one physical block.” [0047])
Regarding Claim 26,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 21, wherein the log buffer is a first log buffer (Command Queue 41-1, Fig. 9), the sequence of logical addresses is a first sequence of logical addresses (“In each command queue, an LBA … may be managed for each write command” [0122])), and the stream of write requests is a first stream of write requests (Stream ID #1 ,Fig. 9); and
wherein the processing device is further configured to:
record (¶0121), into a second log buffer (Command Queue 41-2, Fig. 9), a second sequence of logical addresses associated with second a stream of write requests. (“Each write command includes an LBA of write data, the length of write data, a stream ID, and a data pointer indicative of a location in the write buffer 51 in which write data is stored … each write command including the stream ID #2 is stored in the command queue 41-2” [0119-121]) – Write commands for stream ID #2 and corresponding LBAs are recorded into command queue 41-2.
Regarding Claim 27,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 26, wherein the processing device is further configured to send, to the memory sub-system, the second stream of write requests. (“When the length of write data associated with a set of write commands belonging to a group corresponding to a stream reaches the minimum write size, the write control unit 21 transmits, to the DMAC 15, a transfer request to transfer write data having the minimum write size … the DMAC 15 performs a DMA transfer and thereby transfers the write data having the minimum write size, associated with the stream, from the write buffer 51 in the host memory to the internal buffer. Then, the write control unit 21 sends a program instruction to the NAND interface … to a write destination block in the NAND flash memory 5.” [0125] // Fig. 9) – As previously discussed (see Claim 21 limitation mappings above), once an amount of write data corresponding to the minimum write size is reached for a respective stream, the write data associated with the stream written to NAND.
Regarding Claim 34,
Kanno ‘290 anticipates the following limitations:
An apparatus (Fig. 1), comprising:
a host system (Host 2, Fig. 1) connected to a memory sub-system (SSD 3, Figs. 1 / 2); and a processing device (Controller 4, Fig. 2) configured to:
place a plurality of write requests into a plurality of streams; (“The SSD 3 supports a stream write operation of writing a plurality of types of write data associated with different streams to different blocks, respectively … Each write command sent from the host 2 to the SSD 3 includes a stream identifier (i.e., stream ID) indicative of one of the streams.” [0036-37]) – Each write command received from a host is placed into a corresponding stream via a stream ID included within the write command--
allocate one of a plurality of log buffers (Command Queues 41, Fig. 9) to each one of the plurality of streams; (“the controller 4 classifies the received write commands into n+1 groups corresponding to the streams #1 to #n by storing each received write command in one of command queues 41-1 to 41-n corresponding to the streams #1 to #n” [0110]) – Each stream is associated with a corresponding command queue (i.e., “one of a plurality of log buffers”)-- and
record (¶0121), into each one of the plurality of log buffers, a respective plurality of sequences of logical addresses (“an LBA of write data” [0119]). (“Each write command includes an LBA of write data, the length of write data, a stream ID, and a data pointer indicative of a location in the write buffer 51 in which write data is stored … the write control unit 21 receives write commands from the submission queue of the host 2 and stores each of the received write commands in one of the command queues 41-1 to 41-n, thereby classifying the received write commands into a plurality of groups corresponding to the streams #1 to #n.” [0119-121] // Fig. 9) – Write commands associated with each stream and including respective LBAs (i.e., “a respective plurality of sequences of logical addresses”) are recorded into corresponding command queues 41.
Regarding Claim 35,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 34, the processing device further configured to determine a superblock size associated with superblocks of the memory sub-system. (“A write destination block may be one physical block or one superblock. The structure wherein each superblock includes only one physical block may be adopted. In this case, each superblock is equivalent to one physical block.” [0047] // “the write control unit 21 allocates a plurality of write destination blocks corresponding to a plurality of streams from a plurality of blocks of the NAND flash memory 5, and manages the allocated write destination blocks” [0062]) – Write control unit allocates superblocks, sized according to one physical NAND flash block, to a plurality of streams--
Regarding Claim 37,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 34, wherein the processing device is further configured to
send (¶0125), to the memory sub-system, each of the plurality of streams, wherein each of the plurality of streams causes the memory sub-system to store data associated with the plurality of write requests associated with the plurality of streams. (“When the length of write data associated with a set of write commands belonging to a group corresponding to a stream reaches the minimum write size, the write control unit 21 transmits, to the DMAC 15, a transfer request to transfer write data having the minimum write size … the DMAC 15 performs a DMA transfer and thereby transfers the write data having the minimum write size, associated with the stream, from the write buffer 51 in the host memory to the internal buffer. Then, the write control unit 21 sends a program instruction to the NAND interface … to a write destination block in the NAND flash memory 5.” [0125] // Fig. 9) – Once an amount of write data corresponding to a minimum write size is reached for a respective stream, the write data associated with the stream written to NAND.
Regarding Claim 38,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 34, wherein the processing device is further configured to trim a first stream of the plurality of streams based on a command (“trim command” [0056]) sent by the processing device to the memory sub-system, (“The host interface 11 receives various commands from the host 2. These commands include … a deallocation command (i.e., unmap/trim command)” [0056] // “When all valid data in a block … are invalidated by … deallocation (i.e., unmap/trim) … the controller 4 moves the block to the free block pool 200 and makes the block transition to the state of being reusable as a write destination block” [0099] // Fig. 6) – A host transmits trim commands to the SSD. Trim commands cause data to be invalidated at write destination blocks which store stream data (i.e., “trim a first stream”)--
wherein the command instructs the memory sub-system to erase, according to a superblock size (¶0045), an amount of data from a portion of a sequence of logical addresses recorded in a first log buffer of the plurality of log buffers, (“An erase operation may be executed … in units of a parallel unit (i.e., superblock)” [0045] // “The blocks which include only the invalid data after valid data have been copied to the other block are released as blocks. These blocks thereby become available after an erase operation is executed for these blocks” [0053] // “The deallocation (i.e., unmap/trim command) is a command to invalidate data corresponding to a logical address” [0089] // ¶¶0119-121) – Erase operations are performed in units of a superblock, whereby superblocks which are full of invalidated data (as specified by logical addresses in a trim command; see ¶0089) are erased and are transitioned to free blocks. As previously discussed (see Claim 34 limitation mappings above), write commands and corresponding logical addresses associated with a given stream are recorded into a command queue; and write commands associated with the given stream are written into the same destination superblock. Accordingly, logical addresses which are associated with a superblock of data being invalidated (and subsequently erased) via a trim command would be associated with write commands recorded within the same command queue (i.e., “a first log buffer”)--
wherein the first log buffer is associated with the first stream (¶¶0119-121), and wherein erasure of the amount of data frees at least one superblock in the memory sub-system. (¶¶0045; 0053) – As discussed above, erasure is performed in units of a superblock and enables reuse of destination blocks for new write data.
Regarding Claim 39,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 21, wherein the processing device is further configured to:
identify, based on the superblock size, logical addresses to be erased, (“An erase operation may be executed … in units of a parallel unit (i.e., superblock)” [0045] // “The blocks which include only the invalid data after valid data have been copied to the other block are released as blocks. These blocks thereby become available after an erase operation is executed for these blocks” [0053] // “The deallocation (i.e., unmap/trim command) is a command to invalidate data corresponding to a logical address” [0089]) – Erase operations are performed in units of a superblock, whereby superblocks which are full of invalidated data (as specified by logical addresses in a trim command; see ¶0089) are erased and are transitioned to free blocks--
wherein the logical addresses are associated with data stored in the memory sub-system (¶0051);
send, to the memory sub-system, a command (“a trim command” [0056]) to erase the data stored in the memory sub-system according to the logical addresses identified (“The host interface 11 receives various commands from the host 2. These commands include … a deallocation command (i.e., unmap/trim command) … The deallocation command (i.e., unmap/trim command) is a command to invalidate data corresponding to a logical address. The deallocation command (i.e., unmap/trim command) specifies a logical address range (LBA range) to be invalidated.” [0056-59] // “The blocks which include only the valid data … become available after an erase operation is executed for these blocks” [0053]) – A trim command specifies a range of LBAs to invalidate. As discussed above, when all data within a physical block (and thus a superblock; see ¶0047) becomes invalidated, the physical block is erased and is transitioned to a free block. Examiner accordingly considers a trim command specifying logical addresses as “a command to erase the data” because trim commands invalidate data within a physical block; and physical blocks completely comprised of invalidated data are erased--; and
determine, based on erasure of the data, that a first superblock of the plurality of memory superblocks in the memory sub-system is entirely erased. (“The blocks which include only the invalid data after the valid data have been copied to the other block are released as free blocks. These blocks thereby become available after an erase operation is executed of these blocks” [0053] // Fig. 6) – Once a physical block including only invalidated data is erase, the physical block is transitioned into a free block to indicate the block can again be used as a destination block. Accordingly, transitioning a block to a free block after the block is erased signifies that the corresponding block “is entirely erased” and thus can be used again as a destination for write commands.
Regarding Claim 40,
Kanno ‘290 anticipates the following limitations:
The apparatus of claim 39, wherein the processing device is further configured to reclaim, based on a determination that the first superblock is entirely erased, the superblock for a new stream of data write requests. (“The blocks which include only the invalid data after the valid data have been copied to the other block are released as free blocks. These blocks thereby become available after an erase operation is executed of these blocks” [0053] // “When all valid data in a block in the active block pool 101-n are invalidated by … deallocation (i.e., unmap/trim) … the controller 4 moves the block to the free block pool 200 and makes the block transition to the state of being reusable as a write destination block” [0103] // Fig. 6) – As previously discussed (see Claim 39 limitation mappings above), once a block is erased and is moved back into the free block pool, the block can be used again as another destination block (.e., “for a new stream of data write requests”).
Regarding Claim 41,
Kanno ‘290 anticipates the following limitations:
An apparatus (Fig. 2), comprising:
a memory (DRAM 6, Fig. 2) and a processing device (Controller 4, Fig. 2) configured to: place a plurality of write requests into a plurality of streams; (“The SSD 3 supports a stream write operation of writing a plurality of types of write data associated with different streams to different blocks, respectively … Each write command sent from the host 2 to the SSD 3 includes a stream identifier (i.e., stream ID) indicative of one of the streams.” [0036-37]) – Each write command received from a host is placed into a corresponding stream via a stream ID included within the write command-- and
allocate one of a plurality of log buffers to each one of the plurality of streams. (“it is necessary to prepare a write buffer WB #1, a write buffer WB #2, a write buffer WB #3, … a write buffer WB #n corresponding to the stream #1, the stream #2, the stream #3, …, the stream #n, respectively, in the SSD 3. When a write command including the stream ID #1 is received, write data associated with the write command is transferred from the write buffer in the memory of the host 2 to the write buffer WB #1 … Similarly, whenever a write command including the stream ID #n is received, write data associated with the write command is transferred from the write buffer in the memory of the host 2 to the write buffer WB #n.” [0105-107] // Fig. 7) – Each stream ID is allocated one of a plurality of write buffers (i.e., “a plurality of log buffers’).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 22-24 and 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno ‘290 further in view of an other publication authored by Kanno (US 20210064289 A1)(hereafter referred to as Kanno ‘289).
Regarding Claim 22,
Kanno ‘290 discloses the following limitations:
The apparatus of claim 21 (see Claim 21 limitation mappings above),
Kanno ‘290 is silent regarding how write requests for a given stream are recorded into a command queue and accordingly does not disclose the following limitations:
wherein the sequence of logical addresses are recorded into the log buffer circularly.
However, Kanno ‘289 discloses the following limitations:
wherein the sequence of logical addresses are recorded into the log buffer (SQ #1, Fig. 7) circularly. (“dedicated submission queues SQ #1 to SQ #n (a plurality of write destination blocks), respectively, are allocated in the memory of the host 2. Each of submission queues SQ #1 to SQ #n may be realized by a circular buffer (circular queue)” [0105] // ¶¶0105-116) – Examiner considers the submission queues depicted in Kanno ‘289 Fig. 7 as analogous to the request queues 41 depicted in Kanno ‘290 Fig. 9 because both are request queues which are allocated to respective streams of write commands. As taught in Kanno ‘289, each submission queue including SQ #1 (i.e., “the log buffer”) corresponds to a circular queue. Accordingly, the write commands (including logical addresses; see Kanno ‘290 ¶0119) corresponding to a particular stream are recorded “circularly” into a command queue.
Kanno ‘290 and Kanno ‘289 are considered analogous to the claimed invention because they all relate to the same field of superblock configuration and management within an SSD. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kanno ‘290 with the teachings of Kanno ‘289 and realize an apparatus whereby write commands associated with a particular stream are recorded into a circular queue. Maintaining separate submission queues for respective write streams improves performance by preventing streams of larger amounts of data from being blocked by smaller streams of data, as disclosed in Kanno ‘289 ¶0132: “as write commands corresponding to different streams are not present in the same submission queue, it is possible to prevent a situation (blocking) in which write commands corresponding to a stream having a large amount of write data cannot be fetched from the submission queue by write commands in wait for write corresponding to another stream having a small amount of write data.” [0132]
Regarding Claim 23,
The same motivation to combine provided in Claim 22 is equally applicable to Claim 23. The combined teachings of Kanno ‘290 and Kanno ‘289 disclose the following limitations:
The apparatus of claim 22, wherein, after the log buffer is full, space in the log buffer is reused to continue to record the sequence of logical addresses. (Kanno ‘289, “In a fetch process, one or more write commands are fetched from a submission queue SQ … In a next pointer update process, the host 2 is notified of the submission queue entry in which a fetched write command is stored (the last fetched submission queue entry) by updating the value of the next pointer. In this way, the host 2 is capable of reusing the last fetched submission queue entry for storing another write command.” [0119] // Fig. 7) – As taught in Kanno ‘289, as write commands are fetched from submission queues, corresponding pointers associated with submission queues are updated so as to enable “reusing” of submission queue entries for other write commands.
Regarding Claim 24,
The same motivation to combine provided in Claim 22 is equally applicable to Claim 24. The combined teachings of Kanno ‘290 and Kanno ‘289 disclose the following limitations:
The apparatus of claim 23, wherein a portion of the sequence of logical addresses is deleted or overwritten upon the space in the log buffer being reused. (Kanno ‘289, “the host 2 is capable of reusing the last fetched submission queue entry for storing another write command.” [0119]) – As previously discussed (see Claim 23 limitation mappings above), after a command is fetched from a submission queue, submission queue entries are reused to store other write commands for a stream (i.e., entries are effectively “overwritten” to store another write command).
Regarding Claim 31,
Kanno ‘290 discloses the following limitations:
The apparatus of claim 21 (see Claim 21 limitation mappings above),
Kanno ‘290 is silent regarding head and tail pointers for command queues 41 and accordingly does not disclose the following limitations:
wherein the processing device is further configured to maintain a head pointer that identifies a first location in the log buffer that stores a starting logical block address of the sequence of logical addresses.
However, Kanno ‘289 discloses the following limitations:
wherein the processing device is further configured to maintain a head pointer that identifies a first location in the log buffer that stores a starting logical block address of the sequence of logical addresses. (“dedicated submission queues SQ #1 to SQ #n (a plurality of write destination blocks), respectively, are allocated in the memory of the host 2. Each of submission queues SQ #1 to SQ #n may be realized by a circular buffer (circular queue) … Each of submission queues SQ #1 to SQ #n is controlled by two corresponding pointers (a next pointer and an entrance pointer). The next pointer corresponds to a submission queue head pointer … The next pointer is a pointer indicative of the entry in the submission queue from which the next command should be fetched.” [0105-107] // Fig. 7 // ¶¶0105-116) – Examiner considers the submission queues depicted in Kanno ‘289 Fig. 7 as analogous to the request queues 41 depicted in Kanno ‘290 Fig. 9 because both are request queues which are allocated to respective streams of write commands. As taught in Kanno ‘289, each submission queue including SQ #1 (i.e., “the log buffer”) is controlled by a “next pointer” (i.e., “a head pointer’) which specifies where in the submission queue a next write command (and accordingly a “starting logical address”; see Kanno ‘290 ¶0119) should be fetched from.
Kanno ‘290 and Kanno ‘289 are considered analogous to the claimed invention because they all relate to the same field of superblock configuration and management within an SSD. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kanno ‘290 with the teachings of Kanno ‘289 and realize an apparatus whereby write commands associated with a particular stream are recorded into a command queue which is controlled by a head pointer. Maintaining separate submission queues for respective write streams improves performance by preventing streams of larger amounts of data from being blocked by smaller streams of data, as disclosed in Kanno ‘289 ¶0132: “as write commands corresponding to different streams are not present in the same submission queue, it is possible to prevent a situation (blocking) in which write commands corresponding to a stream having a large amount of write data cannot be fetched from the submission queue by write commands in wait for write corresponding to another stream having a small amount of write data.” [0132]
Regarding Claim 32,
The same motivation to combine provided in Claim 31 is equally applicable to Claim 32. The combined teachings of Kanno ‘290 and Kanno ‘289 disclose the following limitations:
The apparatus of claim 31, wherein the processing device is further configured to maintain a tail pointer that identifies a second location in the log buffer that stores a last logical block address of the sequence of logical addresses. (Kanno ‘289, “Each of submission queues SQ #1 to SQ #n is controlled by two corresponding pointers (a next pointer and an entrance pointer) … The entrance pointer corresponds to a submission queue tail pointer … The entrance pointer is a pointer to indicate the entry in the submission queue in which the next command should be placed.” [0106-107]) -- As taught in Kanno ‘289, each submission queue is controlled by an “entrance pointer” (i.e., “a tail pointer’) which specifies where in the submission queue a next write command (and accordingly a “last logical address”; see Kanno ‘290 ¶0119) should be placed into.
Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno ‘290 further in view of Ko (US 20200012444 A1)(hereafter referred to as Ko).
Regarding Claim 28,
Kanno ‘290 discloses the following limitations:
The apparatus of claim 21 (see Claim 21 limitation mappings above), wherein the sequence of logical addresses recorded into the log buffer comprises at least a first logical address associated with a first superblock and a second logical address (“Each write command includes an LBA of write data … Each write command including the stream ID #1 is stored in the command queue 41-1” [0119-121] // “the write control unit 21 allocates a plurality of write destination blocks corresponding to a plurality of streams” [0062]) – As previously discussed (see Claim 21 limitation mappings above), each write command associated with a particular stream includes a logical address and is recorded within the corresponding command queue; and each stream is associated with at least one corresponding superblock. Accordingly, at least two write commands (i.e., including “a first logical address” and “a second logical address”) associated with a same stream would be recorded within a command queue and would target at least one superblock (i.e., “a first logical address associated with a first superblock”).
Kanno ‘290 does not explicitly disclose an example embodiment whereby a stream is associated with at least two distinct superblocks and thus does not disclose the following limitations:
the sequence of logical addresses … associated with a first superblock and … a second superblock.
However, Ko clarifies that a write stream can be associated with at least two distinct destination blocks and accordingly discloses the following limitations:
the sequence of logical addresses … associated with a first superblock (Physical Block 0, Fig. 9) and … a second superblock. (Physical Block 4, Fig. 9)(“the resource allocator 26 determines which area of the non-volatile memory the stream is located, and allocates each stream to respective positions” [0108] // “The mapping table 29 may record which physical block the stream is allocated to when the stream is allocated … as shown in Fig. 9, the first stream corresponds to physical blocks 0, 4, 8, 12 … and the second stream corresponds to physical blocks 1, 2, 9, 10” [0137-138] // Figs. 6 + 9 // ¶¶0007-10; 0054) – Examiner considers the SSD depicted Ko Fig. 6 as analogous to the SSD depicted in Kanno ‘290 Fig. 2 because both SSD’s are used as destination storage for plural host write streams. As shown in Ko Fig. 9, a single stream (e.g., Stream 1) is allocated to two distinct physical blocks (i.e., at least “a first superblock” and “a second superblock”; see Kanno ‘290 ¶0047). Accordingly, a command queue storing write commands directed to a Stream 1 of Ko would record write commands directed at least to physical blocks 0, 4, 8, and 12.
Kanno ‘290 and Ko are considered analogous to the claimed invention because they all relate to the same field of superblock configuration and management within an SSD. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kanno ‘290 with the teachings of Ko and realize an apparatus whereby a stream of write requests is allocated to at least two distinct destination blocks. Such a “one-to-many” method of mapping streams to superblocks is a feature of an SSD which operates at improved efficiency due to optimized resource allocation, as disclosed in Ko ¶0152: “the solid state drive according to exemplary embodiments of the present inventive concept may execute the memory allocation operation with high efficiency all the time, irrespective of the size of the stream group which changes depending on the number of streams. In addition, for a stream which may be written at relatively low performance, it is possible to implement an optimized resource allocation by adjusting the speed to be low.” [0152]
Regarding Claim 29,
The same motivation to combine provided in Claim 28 is equally applicable to Claim 29. The combined teachings of Kanno ‘290 and Ko disclose the following limitations:
The apparatus of claim 28, wherein the first superblock and the second superblock of the memory sub-system are not contiguous within an address space of the memory sub-system. (Ko, Fig. 9 // “the first stream corresponds to physical blocks 0, 4, 8, 12” [0138] // “the host 1100 may directly specify and transmit the addresses of the physical blocks of each stream as stream information” [0191]) – As shown in Ko Fig. 9, Stream 1 is mapped to physical blocks 0 and 4, which as clarified in ¶0191 correspond to a physical block addresses (i.e., “within an address space of the memory system”). Physical blocks 0 and 4 are “not contiguous” within the physical address space.
Regarding Claim 30,
The same motivation to combine provided in Claim 28 is equally applicable to Claim 30. The combined teachings of Kanno ‘290 and Ko disclose the following limitations:
The apparatus of claim 29, wherein a third superblock (Ko, Block 1, Fig. 9) is between the first superblock and the second superblock in the address space of the memory sub-system. (Ko, “as shown in Fig. 9, the first stream corresponds to physical blocks 0, 4, 8, 12 … and the second stream corresponds to physical blocks 1, 2, 9, 10” [0138]) – As shown in Ko Fig. 9, physical block 1 (i.e., “a third superblock”; see also Kanno ‘290 ¶0047) is “between” blocks 0 and 4 in the physical address space.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Kanno ‘290 further in view of Kanno ‘289 and Ko.
Regarding Claim 33,
The same motivation to combine provided in Claim 32 is equally applicable to Claim 33. The combined teachings of Kanno ‘290 and Kanno ‘289 disclose the following limitations:
The apparatus of claim 32 (see Claim 32 limitation mappings above), wherein a first logical address identified by the head pointer is associated with a first address in a first superblock of the memory sub-system, and wherein a second logical address identified by the tail pointer is associated with a second address (Kanno ‘290, “Each write command includes an LBA of write data … Each write command including the stream ID #1 is stored in the command queue 41-1” [0119-121] // “the write control unit 21 allocates a plurality of write destination blocks corresponding to a plurality of streams” [0062])(Kanno ‘289, ¶¶0105-107) – As previously discussed (see Claim 21 limitation mappings above) and as taught in Kanno ‘290, each write command associated with a particular stream includes a logical address and is recorded within the corresponding command queue; and each stream is associated with at least one corresponding superblock. Accordingly, at least two write commands (i.e., including “a first logical address” and “a second logical address”) associated with a same stream would be recorded within a command queue and would target at least one superblock (i.e., “a first logical address in a first superblock”). As previously discussed (see Claim 32 limitation mappings above) and as taught in Kanno ‘289, each command queue is managed by head and tail pointers pointing at respective write commands (and thus identify respective logical addresses).
Kanno ‘290 and Kanno ‘289 do not explicitly disclose an example embodiment whereby a stream is associated with at least two distinct superblocks and thus does not disclose the following limitations:
a first logical address … is associated with a first address in a first superblock of the memory sub-system, and wherein a second logical address … is associated with a second address in a second superblock of the memory sub-system.
However, Ko clarifies that a write stream can be associated with at least two distinct destination blocks and accordingly discloses the following limitations:
a first logical address … is associated with a first address in a first superblock (Physical Block 0, Fig. 9) of the memory sub-system, and wherein a second logical address … is associated with a second address in a second superblock (Physical Block 4, Fig. 9) of the memory sub-system. (“the resource allocator 26 determines which area of the non-volatile memory the stream is located, and allocates each stream to respective positions” [0108] // “The mapping table 29 may record which physical block the stream is allocated to when the stream is allocated … as shown in Fig. 9, the first stream corresponds to physical blocks 0, 4, 8, 12 … and the second stream corresponds to physical blocks 1, 2, 9, 10” [0137-138] // Figs. 6 + 9 // ¶¶0007-10; 0054) – Examiner considers the SSD depicted Ko Fig. 6 as analogous to the SSD depicted in Kanno ‘290 Fig. 2 because both SSD’s are used as destination storage for plural host write streams. As shown in Ko Fig. 9, a single stream (e.g., Stream 1) is allocated to two distinct physical blocks (i.e., at least “a first superblock” and “a second superblock”; see Kanno ‘290 ¶0047). Accordingly, a command queue storing write commands directed to physical blocks 1 and 4 would have a head pointer associated with a write command directed to physical block 1 and a tail pointer associated with a write command directed to physical block 4.
Kanno ‘290, Kanno ‘289, and Ko are considered analogous to the claimed invention because they all relate to the same field of superblock configuration and management within an SSD. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kanno ‘290 and Kanno ‘289 with the teachings of Ko and realize an apparatus whereby a stream of write requests is allocated to at least two distinct destination blocks. Such a “one-to-many” method of mapping streams to superblocks is a feature of an SSD which operates at improved efficiency due to optimized resource allocation, as disclosed in Ko ¶0152: “the solid state drive according to exemplary embodiments of the present inventive concept may execute the memory allocation operation with high efficiency all the time, irrespective of the size of the stream group which changes depending on the number of streams. In addition, for a stream which may be written at relatively low performance, it is possible to implement an optimized resource allocation by adjusting the speed to be low.” [0152]
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Kanno ‘290 further in view of Wells et al. (US 20190042150 A1)(hereafter referred to as Wells).
Regarding Claim 36,
Kanno ‘290 discloses the following limitations:
The apparatus of claim 35 (see Claim 35 limitation mappings above), wherein the processing device is further configured to determine the superblock size (“A write destination block may be one physical block or one superblock. The structure wherein each superblock includes only one physical block may be adopted. In this case, each superblock is equivalent to one physical block.” [0047]) – As previously discussed (see Claim 35 limitation mappings above), each superblock corresponds to a physical block.
Kanno ‘290 does not disclose when the size for the superblock is configured and thus does not disclose the following limitations:
determine the superblock size during a boot up of the host system.
However, Wells discloses the following limitations:
determine (Fig. 8, step 802) the superblock size during a boot up (Fig. 8, step 802) of the host system. (“In a step 802, firmware of the SSD detects that the SSD is being booted or started up for the first time (i.e., the initial boot up). In a step 804, the firmware reads a configuration file that was previously programmed into the firmware to identify the capacity of each superblock and each isolation region to be created in the non-volatile memory array. The capacity of the superblock is defined by the SSD manufacturer … The capacity of each isolation region defined in the configuration file can be customized to satisfy a user’s requirements” [0058] // Figs. 5a + 7 + 8 // ¶0004) – Examiner considers the SSD depicted in Wells Fig. 7 as analogous to the SSD 3 of Kanno ‘290 Fig. 1. As taught in Wells ¶0004, the SSD stores data on behalf of host devices and accordingly can be considered as part of “the host system”. As taught in Wells, upon the initial boot of an SSD, firmware reads a configuration file to establish manufacturer-defined superblock sizes and to further group superblocks into “isolation regions” which are defined by a user (see Fig. 5a).
Kanno ‘290 and Wells are considered analogous to the claimed invention because they all relate to the same field of superblock configuration and management within an SSD. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kanno ‘290 with the teachings of Wells and realize a method of establishing a superblock size during a boot up for an SSD. Doing so enables superblocks to be grouped into isolation regions, which improves SSD performance, as disclosed in Wells ¶0030: “By configuring the superblocks using the physical blocks from the same non-volatile memory dies in the same channel(s) to form isolation regions … I/O collisions at the non-volatile memory dies and the channel controllers can be minimized or avoided altogether, allowing for lower latency, greater predictability, and more consistent I/O performance of the SSD.” [0030]
Conclusion
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/J.S.M./Examiner, Art Unit 2133
/SEAN D ROSSITER/Primary Examiner, Art Unit 2133
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