Prosecution Insights
Last updated: October 25, 2026
Application No. 19/095,543

SYSTEMS AND METHODS FOR REDUCING INTERNET TRAFFIC LATENCY

Non-Final OA §103
Filed
Mar 31, 2025
Examiner
LEE, BRYAN Y
Art Unit
2445
Tech Center
2400 — Computer Networks
Assignee
Adeia Technologies Inc.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
229 granted / 340 resolved
+9.4% vs TC avg
Strong +41% interview lift
Without
With
+40.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
7 currently pending
Career history
351
Total Applications
across all art units

Statute-Specific Performance

§101
7.2%
-32.8% vs TC avg
§103
56.3%
+16.3% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 340 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The present application is being examined under the pre-AIA first to invent provisions. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. / U.S. Pre-Grant Publication US-20250350563-A1 to Cho et al. (“Cho”) in view of U.S. Patent No. / U.S. Pre-Grant Publication US-20190260681-A1 to Cavaliere et al. (“Cavaliere”). As to claim 1, Cho disclose(s) a method comprising: receiving, at an access network server, data from a transmitting server; (Cho; use plane device receives packets; [0064]) identifying, at the access network server, a data type associated with the data; (Cho; deep packet inspection; [0065]) determining, at the access network server, that the data type is associated with low latency; (Cho; category real-time, ultra-reliable; [0065]) based on, at least in part, the determining that the data type is associated with low latency, determining, at the access network server, a separation distance associated with the access network server and the transmitting server; (Cho; latency budget; [0068]) Cho does not expressly disclose determining, at the access network server, that the separation distance is greater than a distance threshold; applying a low-latency policy to the data; and transmitting the data, from the access network server, to a computing device in accordance with the low-latency policy. determining, at the access network server, that the separation distance is greater than a distance threshold; (Cavaliere; end-to-end latency greater than a threshold; [0076]-[0078]; fig. 5; 504) applying a low-latency policy to the data; (Cavaliere; assign priority based on latency; [0076]-[0078]; fig. 5; 502) and transmitting the data, from the access network server, to a computing device in accordance with the low-latency policy. (Cavaliere; route packet; [0076]-[0078]; fig. 5; 506) At the time of invention, it would have been obvious to a person of ordinary skill in the art to combine the low latency packet determination of Cho and the latency priorities of Cavaliere. One of ordinary skill in the art would have been motivated to combine the teachings as both are concerned with latency. Using the low latency priorities of Cavaliere would allow for low latency applications to be assigned higher priority. Accordingly, the prior art references teach all of the claimed elements. Furthermore, it would have been obvious to combine the teachings as all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable As to claim 11, Cho-Cavaliere disclose(s) a system comprising: input/output circuitry configured to: receive, at an access network server, data from a transmitting server; and processing circuitry configured to: identify, at the access network server, a data type associated with the data; determine, at the access network server, that the data type is associated with low latency; based on, at least in part, the determining that the data type is associated with low latency, determine, at the access network server, a separation distance associated with the access network server and the transmitting server; determine, at the access network server, that the separation distance is greater than a distance threshold; apply a low-latency policy to the data; and transmit the data, from the access network server, to a computing device in accordance with the low-latency policy. See similar rejection and motivation to claim 1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN LEE whose telephone number is (571)270-5606. The examiner can normally be reached on Mon-Fri 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, OSCAR LOUIE can be reached on (571)270-1684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRYAN Y LEE/Primary Examiner, Art Unit 2445
Read full office action

Prosecution Timeline

Mar 31, 2025
Application Filed
Oct 06, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+40.7%)
3y 11m (~2y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 340 resolved cases by this examiner. Grant probability derived from career allowance rate.

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