DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 21 recites, “transfer the decrypted and authenticated data from the first buffer into memory of the graphics processor hardware circuitry” and claims 29 and 26 recites similar limitations. Please note that claim recites “decrypt the encrypted data into decrypted data” and “authenticate the encrypted data…”. There is no disclosure of sending any authenticated data along with the decrypted data in the originally filed disclosure. Specification at paragraph 0213 recites, “The App 1410 reads 1512 the data from the sharedMEM 1420 and decrypts 1513 and calculates a MAC as it brings the data from sharedMEM 1420 to private memory. The App 1410 consumes the data when it has verified 1514 if the MAC calculated on the local buffer 1420 matches the MAC received from the device 1460”. As a result, transferring of authenticated data along with the decrypted data is not supported by the original discloser. Correction/Clarification is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites, “transfer the decrypted and authenticated data from the first buffer into memory of the graphics processor hardware circuitry” and claims 29 and 26 recites similar limitations. Please note that claim recites “decrypt the encrypted data into decrypted data” and “authenticate the encrypted data…”. It is not clear what is the authenticated data is referring to. The claims are authenticating the encrypted data and it is not clear if the encrypted data is being transferred along with decrypted data or another form of authenticated data is being transferred along with decrypted data. Correction/Clarification is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,289,301 B2 in view of Chhabra et al. (US 2020/0052892 A1), hereinafter, “Chhabra”.
Claims 21-40 requires following additional limitation: graphic processor hardware circuitry to:
decrypt the encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry.
Chhabra discloses graphic processor hardware circuitry for decrypting an encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry (See, Paragraphs 0083, 0084, 0086 and 0095).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the graphic processor hardware circuitry for decrypting an encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry as taught by Chhabra because “[T]the employment of composite/accumulated MAC for employment of authenticated AES/GCM encryption to contribute to providing reduced or no latency link encryption” (See, Chhabra, Paragraph 0053).
Claims 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,149,513 B2 in view of Chhabra.
Claims 21-40 requires following additional limitation: graphic processor hardware circuitry to:
decrypt the encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry.
Chhabra discloses graphic processor hardware circuitry for decrypting an encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry (See, Paragraphs 0083, 0084, 0086 and 0095).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the graphic processor hardware circuitry for decrypting an encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry as taught by Chhabra because “[T]the employment of composite/accumulated MAC for employment of authenticated AES/GCM encryption to contribute to providing reduced or no latency link encryption” (See, Chhabra, Paragraph 0053).
Claims 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,784,990 B2 in view of Chhabra.
Claims 21-40 requires following additional limitation: graphic processor hardware circuitry to:
decrypt the encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry.
Chhabra discloses graphic processor hardware circuitry for decrypting an encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry (See, Paragraphs 0083, 0084, 0086 and 0095).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the graphic processor hardware circuitry for decrypting an encrypted data into decrypted data and transfer the decrypted and authentication data from a first buffer into memory of the graphic processor hardware circuitry as taught by Chhabra because “[T]the employment of composite/accumulated MAC for employment of authenticated AES/GCM encryption to contribute to providing reduced or no latency link encryption” (See, Chhabra, Paragraph 0053).
Allowable Subject Matter
Claims 21-40 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) and 35 U.S.C. 112(a), set forth in this Office action and by filing terminal disclaimer to overcome the non-statutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (WO 2020/000401 A1).
Li et al. (US 2020/0220713 A1).
Ayoub (US 2014/0258438 A1).
Tshirkin et al. (US 2022/0103349 A1).
Smith et al. (US 2020/0242258 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YOGESH PALIWAL whose telephone number is (571)270-1807. The examiner can normally be reached M-F 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Mehrmanesh can be reached at (571)270-3351. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YOGESH PALIWAL/ Primary Examiner, Art Unit 2435
Prosecution Insights