DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 03/31/2025 are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-8, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwok (US 20160283325 A1) in view of Flynn et al (US 20090287956 A1), hereinafter referred as Flynn in further view of Nerl et al 9US 20050289402 A1), hereinafter referred as Nerl.
As per claim 1, Kwok substantially teaches a system comprising:
a plurality of memory components and a processing device, operatively coupled with the plurality of memory components, to perform operations comprising (a computing system may include one or more processors 105 and computer memory including a plurality of memory devices. In FIG. 1 the plurality of memory devices include n memory devices illustrated as memory device 1 110, memory device 2 112, memory device 3 114, and continuing to memory device (n-2) 116, memory device (n-1) 118, and memory device n; Kwok p. 0018):
receiving, from a host system, a request to read data stored on the plurality of memory components (a complete codeword is read 502, wherein the codeword is read from a plurality of memory devices, portions of the codeword being spread among the plurality of memory devices (host is not expressly taught) ; Kwok p. 0078);
determining that the data contains a plurality of errors (The received complete codeword is provided to a syndrome calculator 506, resulting in a partial syndromes S.sub.1, . . . , S.sub.2t. The partial syndromes are provided to a BMA 510, which generates an error locator polynomial; Kwok p. 0078)(a process further includes continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations; Kwok p. 0061) (the received codeword in polynomial form, t is the number of correctable errors, j.sub.1, j.sub.2, etc., are the error locations, and e.sub.1, e.sub.2, etc., are the error values; Kwok p. 0026);
identifying a plurality of locations of the plurality of errors wherein each location of plurality of locations corresponds to a respective error of the plurality of errors (continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations using standard algorithms; Kwok p. 0061)(The roots of σ(x), x=α.sup.−j0, α.sup.−j1, α.sup.−j2, . . . are provided to a logic for finding error location j for each…he values of j.sub.0, j.sub.1, j.sub.2, . . . , are the error locations; Kwok p. 0078);
As stated above, Kwok teaches assuming a failed device. Although that is enough for obviousness, it does not explicitly say that all identified error locations belong to a memory device.
However, Flynn in an analogous art teaches receiving, from a host system, a request to read data stored on the plurality of memory components (as Kwok taught as well) (a subsequent read includes one of a read initiated by a storage region testing module and a read from a read request; Flynn p. 0016) (A computer 112 may be a host, a server, a storage controller of a storage area network…the solid-state storage device 102 operates autonomously to service data requests sent from the computer; Flynn p. 0065)("Receive request to read data”; Flynn FIG. 7-8);
determining that the data contains a plurality of errors (The ECC module determines, using an error correcting code ("ECC"), if one or more errors exist in tested data, and if the errors are correctable using the ECC, the tested data including data read by the read module; Flynn p. 0009).
responsive to determining that the plurality of locations falls in a single memory component of the plurality of memory components, excluding the single memory component from future decoding and correcting the data to generate corrected data (The isolation module selects a memory device from the array of memory devices in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC. The isolation module also replaces data read from the selected memory device with data comprising data generated from the parity data stored on the one or more extra memory devices ("replacement data") and data read from the memory devices that are not selected ("available data") wherein the tested data tested by the ECC module further includes the available data combined with the replacement data (the selected memory device is no longer contributing its own data instead subsiitued by parity-generated replacement data equating to excluding.); Flynn p. 0010; FIG 13) (the apparatus includes a correct data module that returns corrected data in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC; Flynn p. 0022).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kwok with the teachings of Flynn by configuring excluding the single memory component from future decoding and correcting the data to generate corrected data.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ exclusion of the memory component from decoding in the system of Kwok because Flynn teaches an isolation module selects a memory device in response to the ECC module determining those errors exists to provide a level of protection against data errors and device failures, as parity data stored in the array can be used to replace failed data (Flynn p. 0003).
Kwok in view of Flynn, as combined above, also do not teach sending, to the host system, the corrected data; and including the single memory component for future decoding.
However, Nerl in an analogous art teaches sending, to the host system, the corrected data; and including the single memory component for future decoding (The software algorithm may activate the erasure mode by setting appropriate registers of the memory controller of the memory subsystem. The memory subsystem responds by decoding ECC code words from the domain of the memory subsystem by assuming that the identified bits within the ECC code words are corrupted. By decoding ECC code words in this manner, no further page deallocation operations will occur for the respective repeatable error (this equates to including the single memory component for future decoding)….some embodiments remove entries from the page deallocation table upon activation of the erasure mode. Specifically, when an erasure mode is activated for a particular domain and a bit pattern…There is no necessity of retaining those locations in the table, because the erasure mode will cause ECC code words to be decoded without utilizing the bits associated with multiple instances of data corruption; Nerl p. 0017-0018).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kwok in view of Flynn with the teachings of Nerl by configuring sending, to the host system, the corrected data; and including the single memory component for future decoding.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ sending the corrected data and including the memory decoding for future decoding in the system of Kwok in view of Flynn because Nerl teaches restoring normal operation once erasure-mode decoding is available so that a greater number of errors may be sustained before firmware resources are consumed thereby enabling system operations to continue (Nerl p. 0018).
As per claim 4, Kwok in view of Flynn in further view of Nerl teaches the system of claim 1,
wherein determining that the data contains the plurality of errors further comprises:
decoding the data using an error correction code (ECC) decoding operation (the computing system 100 includes logic to decode errors and erasures of the plurality of memory devices based on the partial codeword; Kwok p. 0022)(Reed-Solomon is an error correction code (ECC) that allows for errors and erasures decoding. An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024);
and determining that the plurality of errors cannot be corrected by the error correction code (ECC) decoding operation (the logic further provides for reading the complete codeword upon determining that errors and erasures in the plurality of memory devices cannot be decoded from the partial codeword; Kwok p. 0023) (the incomplete Reed-Solomon codeword is not correctable by utilizing the reduced codeword, the remaining data is read from the skipped memory device, and error correction is repeated with the full strength Reed-Solomon decoding using the full Reed-Solomon codeword; Kwok p. 0054)
As per claim 5, Kwok in view of Flynn in further view of Nerl teaches the system of claim 4,
wherein determining that the plurality of errors cannot be corrected by the error correction code (ECC) decoding operation further comprises:
determining whether a number of the plurality of errors exceeds a maximum number of errors that can be corrected by the error correction code (ECC) decoding operation (In an operation, let A be a number of errors, B be a number of erasures, and t be a maximum number of symbol corrections when there are errors only and no erasures. In such operation the degree of error locator polynomial σ(x) is A, the degree of erasure locator polynomial β(x) is B, and 2A+B≦2t; Kwok p. 0044) (Reed-Solomon is an error correction code (ECC) that allows for errors and erasures decoding. An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024) (if a decode fails, an apparatus, system, or process provides for reading the remainder of the Reed-Solomon codeword from the unread memory device and decoding using the full decoding power without erasures; Kwok p. 0063).
As per claim 6, Kwok in view of Flynn in further view of Nerl teaches the system of claim 1,
wherein correcting the data to generate the corrected data is performed using an error correction code (ECC) decoding operation (Reed-Solomon is an error correction code (ECC) that allows for errors and erasures decoding. An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024) (logic to decode errors and erasures of the plurality of memory devices based on the partial codeword; Kwok p. 0022).
As per claim 7, Kwok in view of Flynn in further view of Nerl teaches the system of claim 1, wherein the data comprises a plurality of symbols, and wherein each of the plurality of symbols contains a respective error of the plurality of errors (An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024)(continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations using standard algorithms such as the Berlekamp-Massey Algorithm (BMA), the Euclidean Algorithm, the Peterson-Gorenstein-Zierler algorithm, or other fast methods to solve for 1 or 2 errors.; Kwok p. 0061, 0078).
As per claim 8, Kwok in view of Flynn in further view of Nerl teaches the system of claim 1,
wherein each of the plurality of memory components is a die (a storage region comprises one or more of one or more ECC chunks, one or more physical pages, one or more logical pages, one or more physical erase blocks, one or more logical erase blocks, a chip, a portion of a chip, a portion of one or more dies, and one or more dies; Flynn p. 0016).
As per claim 17, teaches a non-transitory computer-readable storage medium (a non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations including. storing a portion of an error correction codeword in each of a plurality of memory devices; and decoding errors and erasures of the plurality of memory devices, wherein the decoding of the errors and erasures includes: reading the portions of the error correction codeword from a first subset of the plurality of memory devices to generate a partial codeword, the first subset excluding at least one of the plurality of memory devices, and decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword; Kwok p. 0133) comprising
instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving, from a host system, a request to read data stored on a plurality of memory components (a complete codeword is read 502, wherein the codeword is read from a plurality of memory devices, portions of the codeword being spread among the plurality of memory devices (host is not expressly taught) ; Kwok p. 0078);
determining that the data contains a plurality of errors (The received complete codeword is provided to a syndrome calculator 506, resulting in a partial syndromes S.sub.1, . . ., S.sub.2t. The partial syndromes are provided to a BMA 510, which generates an error locator polynomial; Kwok p. 0078)(a process further includes continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations; Kwok p. 0061) (the received codeword in polynomial form, t is the number of correctable errors, j.sub.1, j.sub.2, etc., are the error locations, and e.sub.1, e.sub.2, etc., are the error values; Kwok p. 0026);
identifying a plurality of locations of the plurality of errors, wherein each location of plurality of locations corresponds to a respective error of the plurality of errors (continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations using standard algorithms; Kwok p. 0061)(The roots of σ(x), x=α.sup.−j0, α.sup.−j1, α.sup.−j2, . . . are provided to a logic for finding error location j for each…he values of j.sub.0, j.sub.1, j.sub.2, . . . , are the error locations; Kwok p. 0078)
As stated above, Kwok teaches assuming a failed device. Although that is enough for obviousness, it does not explicitly say that all identified error locations belong to a memory device.
However, Flynn in an analogous art teaches receiving, from a host system, a request to read data stored on the plurality of memory components (as Kwok taught as well) (a subsequent read includes one of a read initiated by a storage region testing module and a read from a read request; Flynn p. 0016) (A computer 112 may be a host, a server, a storage controller of a storage area network…the solid-state storage device 102 operates autonomously to service data requests sent from the computer; Flynn p. 0065)("Receive request to read data”; Flynn FIG. 7-8);
determining that the data contains a plurality of errors (The ECC module determines, using an error correcting code ("ECC"), if one or more errors exist in tested data, and if the errors are correctable using the ECC, the tested data including data read by the read module; Flynn p. 0009).
responsive to determining that the plurality of locations falls in a single memory component of the plurality of memory components, excluding the single memory component from future decoding and correcting the data to generate corrected data (The isolation module selects a memory device from the array of memory devices in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC. The isolation module also replaces data read from the selected memory device with data comprising data generated from the parity data stored on the one or more extra memory devices ("replacement data") and data read from the memory devices that are not selected ("available data") wherein the tested data tested by the ECC module further includes the available data combined with the replacement data (the selected memory device is no longer contributing its own data instead subsiitued by parity-generated replacement data equating to excluding.); Flynn p. 0010; FIG 13) (the apparatus includes a correct data module that returns corrected data in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC; Flynn p. 0022).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kwok with the teachings of Flynn by configuring excluding the single memory component from future decoding and correcting the data to generate corrected data.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ exclusion of the memory component from decoding in the system of Kwok because Flynn teaches an isolation module selects a memory device in response to the ECC module determining those errors exists to provide a level of protection against data errors and device failures, as parity data stored in the array can be used to replace failed data (Flynn p. 0003).
Kwok in view of Flynn, as combined above, also do not teach sending, to the host system, the corrected data; and including the single memory component for future decoding.
However, Nerl in an analogous art teaches sending, to the host system, the corrected data; and including the single memory component for future decoding (The software algorithm may activate the erasure mode by setting appropriate registers of the memory controller of the memory subsystem. The memory subsystem responds by decoding ECC code words from the domain of the memory subsystem by assuming that the identified bits within the ECC code words are corrupted. By decoding ECC code words in this manner, no further page deallocation operations will occur for the respective repeatable error (this equates to including the single memory component for future decoding)….some embodiments remove entries from the page deallocation table upon activation of the erasure mode. Specifically, when an erasure mode is activated for a particular domain and a bit pattern…There is no necessity of retaining those locations in the table, because the erasure mode will cause ECC code words to be decoded without utilizing the bits associated with multiple instances of data corruption; Nerl p. 0017-0018).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kwok in view of Flynn with the teachings of Nerl by configuring sending, to the host system, the corrected data; and including the single memory component for future decoding.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ sending the corrected data and including the memory decoding for future decoding in the system of Kwok in view of Flynn because Nerl teaches restoring normal operation once erasure-mode decoding is available so that a greater number of errors may be sustained before firmware resources are consumed thereby enabling system operations to continue (Nerl p. 0018).
As per claim 20, Kwok in view of Flynn in further view of Nerl teaches the non-transitory computer-readable storage medium of claim 17,
wherein determining that the data contains the plurality of errors further comprises:
decoding the data using an error correction code (ECC) decoding operation (the computing system 100 includes logic to decode errors and erasures of the plurality of memory devices based on the partial codeword; Kwok p. 0022)(Reed-Solomon is an error correction code (ECC) that allows for errors and erasures decoding. An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024);
and determining that the plurality of errors cannot be corrected by the error correction code (ECC) decoding operation (the logic further provides for reading the complete codeword upon determining that errors and erasures in the plurality of memory devices cannot be decoded from the partial codeword; Kwok p. 0023) (the incomplete Reed-Solomon codeword is not correctable by utilizing the reduced codeword, the remaining data is read from the skipped memory device, and error correction is repeated with the full strength Reed-Solomon decoding using the full Reed-Solomon codeword; Kwok p. 0054).
Claims 2-3, 9-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kwok in view of Flynn in further view of Nerl in further view of Kuzmin et al (US 11544183 B1), hereinafter referred as Kuzmin.
As per claim 2, Kwok in view of Flynn in further view of Nerl teaches the system of claim 1, the operations further comprise: marking an address of the plurality of locations of the single memory component;
responsive to receiving a second request specifying the address, determining whether the address is marked;
and responsive to determining that the address is marked, determining that a set of locations corresponding to the address is known to contain one or more errors.
However, Kuzmin in an analogous art teaches the system of claim 1, the operations further comprise: marking an address of the plurality of locations of the single memory component (The memory controller tracks subdivision-specific-usage data using internal storage 111. In one embodiment, this storage can be volatile memory such as synchronous random access memory (SRAM); in another embodiment, this storage can be non-volatile memory, for example an internal flash array. As denoted by reference numeral 113, the storage retains information for each subdivision of the memory governed by the memory controller, in this case, for a physical subdivision of the memory 107. In embodiments where the memory 107 is a NAND flash memory, the storage retains information for each EU or physical page of the flash memory(subdivision specific physical memory equates addresses); Kuzmin Col.8 lines 21-32) (for each subdivision by the memory controller can optionally include one or more of: whether the respective subdivision has been marked as bad; Kuzmin Col.7 lines 19-23);
responsive to receiving a second request specifying the address, determining whether the address is marked (the host sends 10 requests to the memory controller that directly specify physical address; Kuzmin Col.10 lines 38-39) (the host can request (a) return of raw information for the entire memory space managed by the memory controller, or for specific address ranges; Col.11 lines 62-65) (whether the respective subdivision has been marked as bad; Kuzmin Col.7 lines 19-23);
and responsive to determining that the address is marked, determining that a set of locations corresponding to the address is known to contain one or more errors (Pages found defective due to write error are remapped by defect remapping logic 385, with write operation retried transparent to the host. The original page in error is marked defective or “bad” and added to a bad block list or map to avoid further use of associated physical pages; Kuzmin Col.17 lines 31-35).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Kwok in view of Flynn in further view of Nerl with the teachings of Kuzmin by configuring marking an address of the plurality of locations of the single memory component.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ specifying and marking an address in the system of Kwok in view of Flynn in further view of Nerl because Kuzmin teaches specifying addresses for pertinent memory operations to improve the efficiency with which memory is used and also help better distribute wear (Kuzmin Col.23 lines 3-6).
As per claim 3, Kwok in view of Flynn in further view of Nerl in further view of Kuzmin teaches the system of claim 2,
wherein the request specifies the address (the host sends 10 requests to the memory controller that directly specify physical address; Kuzmin Col.10 lines 38-39).
As per claim 9, Kwok in view of Flynn in further view of Nerl in further view of Kuzmin teaches a method comprising:
receiving, by a processing device, from a host system, a request to read data stored on a plurality of memory components (a computing system may include one or more processors 105 and computer memory including a plurality of memory devices. In FIG. 1 the plurality of memory devices include n memory devices illustrated as memory device 1 110, memory device 2 112, memory device 3 114, and continuing to memory device (n-2) 116, memory device (n-1) 118, and memory device n; Kwok p. 0018)(a complete codeword is read 502, wherein the codeword is read from a plurality of memory devices, portions of the codeword being spread among the plurality of memory devices (host is not expressly taught) ; Kwok p. 0078) (a subsequent read includes one of a read initiated by a storage region testing module and a read from a read request; Flynn p. 0016) (A computer 112 may be a host, a server, a storage controller of a storage area network…the solid-state storage device 102 operates autonomously to service data requests sent from the computer; Flynn p. 0065)("Receive request to read data";Flynn FIG. 7-8);
determining that the data contains a plurality of errors (The received complete codeword is provided to a syndrome calculator 506, resulting in a partial syndromes S.sub.1, . . . , S.sub.2t. The partial syndromes are provided to a BMA 510, which generates an error locator polynomial; Kwok p. 0078)(a process further includes continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations; Kwok p. 0061) (the received codeword in polynomial form, t is the number of correctable errors, j.sub.1, j.sub.2, etc., are the error locations, and e.sub.1, e.sub.2, etc., are the error values; Kwok p. 0026) (The ECC module determines, using an error correcting code ("ECC"), if one or more errors exist in tested data, and if the errors are correctable using the ECC, the tested data including data read by the read module; Flynn p. 0009);
identifying a plurality of locations of the plurality of errors, wherein each location of plurality of locations corresponds to a respective error of the plurality of errors (continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations using standard algorithms; Kwok p. 0061)(The roots of σ(x), x=α.sup.−j0, α.sup.−j1, α.sup.−j2, . . . are provided to a logic for finding error location j for each…he values of j.sub.0, j.sub.1, j.sub.2, . . . , are the error locations; Kwok p. 0078);
responsive to determining that the plurality of locations are associated with a single memory component of the plurality of memory components, correcting the data to generate corrected data (The isolation module selects a memory device from the array of memory devices in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC. The isolation module also replaces data read from the selected memory device with data comprising data generated from the parity data stored on the one or more extra memory devices ("replacement data") and data read from the memory devices that are not selected ("available data") wherein the tested data tested by the ECC module further includes the available data combined with the replacement data (the selected memory device is no longer contributing its own data instead subsiitued by parity-generated replacement data equating to excluding.); Flynn p. 0010; FIG 13) (the apparatus includes a correct data module that returns corrected data in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC; Flynn p. 0022);
sending the corrected data to the host system (The software algorithm may activate the erasure mode by setting appropriate registers of the memory controller of the memory subsystem. The memory subsystem responds by decoding ECC code words from the domain of the memory subsystem by assuming that the identified bits within the ECC code words are corrupted. By decoding ECC code words in this manner, no further page deallocation operations will occur for the respective repeatable error (this equates to including the single memory component for future decoding)….some embodiments remove entries from the page deallocation table upon activation of the erasure mode. Specifically, when an erasure mode is activated for a particular domain and a bit pattern…There is no necessity of retaining those locations in the table, because the erasure mode will cause ECC code words to be decoded without utilizing the bits associated with multiple instances of data corruption; Nerl p. 0017-0018);
and marking an address of the plurality of locations associated with the single memory component, wherein the marking is to indicate, in future decoding, that an error was detected at the plurality of locations (the host sends 10 requests to the memory controller that directly specify physical address; Kuzmin Col.10 lines 38-39) (the host can request (a) return of raw information for the entire memory space managed by the memory controller, or for specific address ranges; Col.11 lines 62-65) (whether the respective subdivision has been marked as bad; Kuzmin Col.7 lines 19-23)(Pages found defective due to write error are remapped by defect remapping logic 385, with write operation retried transparent to the host. The original page in error is marked defective or “bad” and added to a bad block list or map to avoid further use of associated physical pages; Kuzmin Col.17 lines 31-35).
As per claim 10, Kwok in view of Flynn in further view of Nerl teaches the method of claim 9, further comprising:
responsive to receiving a second request specifying the address, determining whether the address is marked (the host sends 10 requests to the memory controller that directly specify physical address; Kuzmin Col.10 lines 38-39) (the host can request (a) return of raw information for the entire memory space managed by the memory controller, or for specific address ranges; Col.11 lines 62-65) (whether the respective subdivision has been marked as bad; Kuzmin Col.7 lines 19-23);
and responsive to determining that the address is marked, determining that a set of locations corresponding to the address is known to contain one or more errors (Pages found defective due to write error are remapped by defect remapping logic 385, with write operation retried transparent to the host. The original page in error is marked defective or “bad” and added to a bad block list or map to avoid further use of associated physical pages; Kuzmin Col.17 lines 31-35).
As per claim 11, Kwok in view of Flynn in further view of Nerl teaches the method of claim 9,
wherein the request specifies the address (the host sends 10 requests to the memory controller that directly specify physical address; Kuzmin Col.10 lines 38-39).
As per claim 12, Kwok in view of Flynn in further view of Nerl teaches the method of claim 9,
wherein determining that the data contains the plurality of errors further comprises:
decoding the data using an error correction code (ECC) decoding operation (the computing system 100 includes logic to decode errors and erasures of the plurality of memory devices based on the partial codeword; Kwok p. 0022)(Reed-Solomon is an error correction code (ECC) that allows for errors and erasures decoding. An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024);
and determining that the plurality of errors cannot be corrected by the error correction code (ECC) decoding operation (the logic further provides for reading the complete codeword upon determining that errors and erasures in the plurality of memory devices cannot be decoded from the partial codeword; Kwok p. 0023) (the incomplete Reed-Solomon codeword is not correctable by utilizing the reduced codeword, the remaining data is read from the skipped memory device, and error correction is repeated with the full strength Reed-Solomon decoding using the full Reed-Solomon codeword; Kwok p. 0054).
As per claim 13, Kwok in view of Flynn in further view of Nerl teaches the method of claim 12,
wherein determining that the plurality of errors cannot be corrected by the error correction code (ECC) decoding operation further comprises:
determining whether a number of the plurality of errors exceeds a maximum number of errors that can be corrected by the error correction code (ECC) decoding operation (In an operation, let A be a number of errors, B be a number of erasures, and t be a maximum number of symbol corrections when there are errors only and no erasures. In such operation the degree of error locator polynomial σ(x) is A, the degree of erasure locator polynomial β(x) is B, and 2A+B≦2t; Kwok p. 0044) (Reed-Solomon is an error correction code (ECC) that allows for errors and erasures decoding. An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024) (if a decode fails, an apparatus, system, or process provides for reading the remainder of the Reed-Solomon codeword from the unread memory device and decoding using the full decoding power without erasures; Kwok p. 0063).
As per claim 14, Kwok in view of Flynn in further view of Nerl teaches the method of claim 9,
wherein correcting the data to generate the corrected data is performed using an error correction code (ECC) decoding operation (Reed-Solomon is an error correction code (ECC) that allows for errors and erasures decoding. An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024) (logic to decode errors and erasures of the plurality of memory devices based on the partial codeword; Kwok p. 0022).
As per claim 15, Kwok in view of Flynn in further view of Nerl teaches the method of claim 9, wherein the data comprises a plurality of symbols, and wherein each of the plurality of symbols contains a respective error of the plurality of errors (An erasure is a codeword symbol that is marked as being very unreliable; Kwok p. 0024)(continuing decoding the Reed-Solomon codeword using the modified Reed-Solomon syndrome to find the error locations using standard algorithms such as the Berlekamp-Massey Algorithm (BMA), the Euclidean Algorithm, the Peterson-Gorenstein-Zierler algorithm, or other fast methods to solve for 1 or 2 errors.; Kwok p. 0061, 0078).
As per claim 16, Kwok in view of Flynn in further view of Nerl teaches the method of claim 9,
wherein each of the plurality of memory components is a die (a storage region comprises one or more of one or more ECC chunks, one or more physical pages, one or more logical pages, one or more physical erase blocks, one or more logical erase blocks, a chip, a portion of a chip, a portion of one or more dies, and one or more dies; Flynn p. 0016).
As per claim 18, Kwok in view of Flynn in further view of Nerl in further view of Kuzmin teaches the non-transitory computer-readable storage medium of claim 17, the operations further comprise: marking an address of the plurality of locations of the single memory component (The memory controller tracks subdivision-specific-usage data using internal storage 111. In one embodiment, this storage can be volatile memory such as synchronous random access memory (SRAM); in another embodiment, this storage can be non-volatile memory, for example an internal flash array. As denoted by reference numeral 113, the storage retains information for each subdivision of the memory governed by the memory controller, in this case, for a physical subdivision of the memory 107. In embodiments where the memory 107 is a NAND flash memory, the storage retains information for each EU or physical page of the flash memory (subdivision specific physical memory equates addresses); Kuzmin Col.8 lines 21-32) (for each subdivision by the memory controller can optionally include one or more of: whether the respective subdivision has been marked as bad; Kuzmin Col.7 lines 19-23);
responsive to receiving a second request specifying the address, determining whether the address is marked (the host sends 10 requests to the memory controller that directly specify physical address; Kuzmin Col.10 lines 38-39) (the host can request (a) return of raw information for the entire memory space managed by the memory controller, or for specific address ranges; Col.11 lines 62-65) (whether the respective subdivision has been marked as bad; Kuzmin Col.7 lines 19-23);
and responsive to determining that the address is marked, determining that a set of locations corresponding to the address is known to contain one or more errors (Pages found defective due to write error are remapped by defect remapping logic 385, with write operation retried transparent to the host. The original page in error is marked defective or “bad” and added to a bad block list or map to avoid further use of associated physical pages; Kuzmin Col.17 lines 31-35).
As per claim 19, Kwok in view of Flynn in further view of Nerl teaches the non-transitory computer-readable storage medium of claim 18,
wherein the request specifies the address (the host sends 10 requests to the memory controller that directly specify physical address; Kuzmin Col.10 lines 38-39).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
Betz et al. (US 20220066868 A1) teaches a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.
Lastras-Montano et al (US 20100287436 A1) teaches a system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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