DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1, 3-10, and 12-20 are pending.
Response to Arguments
The Objection to the drawings is withdrawn.
The Objection to Claim 1 is withdrawn.
The remainder of Applicant's arguments filed 21 May 2026 have been fully considered but they are not persuasive.
Regarding Claim 1. Applicant argues that Jeong (US 2012/0019498) in view of Qian fails to teach “a drain of the third transistor is grounded” because Jeon teaches the third transistor (fig. 5 @T4) drain is connected to ELVSS (fig. 5 @ELVSS).
The Examiner respectfully disagrees with Applicant’s statement. The following Patent Applications discuss the use of ELVSS in pixel circuits:
Gupta (US 2018/0033805)
[0036] In an organic light-emitting diode display, each display pixel contains a respective organic light-emitting diode. A schematic diagram of an illustrative organic light-emitting diode display pixel 22-1 is shown in FIG. 2. As shown in FIG. 2, display pixel 22-1 may include light-emitting diode 26. A positive power supply voltage ELVDD may be supplied to positive power supply terminal 34 and a ground power supply voltage ELVSS may be supplied to ground power supply terminal 36. The state of drive transistor 28 controls the amount of current flowing through diode 26 and therefore the amount of emitted light 40 from display pixel 22-1.
Lee (US 2025/0193980)
[0041] The inverter 140 may include a first drive element DRT.sub.INV1 of a first polarity and a second drive element DRT.sub.INV2 of a second polarity, which are connected in series between the first power supply voltage ELVDD1 and the ground voltage ELVSS.
Song (US 2023/0317012)
[0138] The light emitting element ED may include an anode electrode AE, a light emitting layer EL, and a cathode electrode CE. The anode electrode AE may be a pixel electrode disposed in each of the sub-pixels SP, and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP. The cathode electrode CE may be a common electrode commonly disposed in the plurality of sub-pixels SP, and a ground voltage ELVSS may be applied to the cathode electrode CE.
In electronics, VSS stands for Voltage at the Source. It typically represents the negative power supply rail or the common ground reference point (0V) in circuits built with Field-Effect Transistors (FETs) or CMOS digital logic.
Applicant has amended figure 2 and their specification to indicate that the drain of T3 is connected to GND and the OLED cathode is connected to VSS. VSS and GND are synonyms as evidenced by Applicant’s disclosure:
[0043] the drain of the third transistor T3 is grounded.
[0055] The source and drain of the third transistor T3 are connected to the drain of the driving transistor TD and VSS respectively.
There is no contradiction in this disclosure because VSS is synonymous with ground. The drain of the third transistor T3 and the cathode of the OLED are both connected to VSS or Ground.
Similarly, Jeon teaches the drain of a third transistor (fig. 5 @T4) and the cathode of the OLED are both connected to ELVSS (fig. 5). Since the prior art considers ELVSS a ground voltage, Jeon teaches a drain of the third transistor is connected to ground.
Applicant also states that Jeon does not teach “an amplitude of the first data signal is less than an amplitude of a signal provided by the data signal input end in the discharge phase”.
The Examiner respectfully disagrees with Applicant’s statement. In figure 6 Jeon teaches a data signal amplitude (Vdata) and a signal in the discharge phase (Vsus). Figure 6 illustrates that Vdata is less that the amplitude of Vsus.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each Claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-10, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2012/0019498) in view of Qian (CN 115331633). All reference is to Jeong unless otherwise indicated.
Regarding Claims 1 and 16 (Currently Amended), Jeong teaches a pixel circuit and a control method for the pixel circuit, comprising:
a light-emitting circuit [fig. 2 @OLED] connected to a driving circuit [fig. 2 @T1], wherein
the light-emitting circuit is configured to emit light or to be turned off according to a driving current provided by the driving circuit [¶0056, “The first transistor T1 controls a driving current that is supplied to the organic light emitting diode (OLED)”];
the driving circuit comprising a driving transistor [fig. 2 @T1], wherein
the driving transistor [fig. 2 @T1] is connected to a data signal input end of the pixel circuit [fig. 2@N1], a power input end [fig. 2 @N2] and the light-emitting circuit [fig. 2 @Vd]; and
the driving transistor is configured to control the light-emitting circuit to emit light or to be turned off [¶0074] according to a signal input by the data signal input end [fig. 3 @data signal is Vsus or Vdata];
a compensation circuit [fig. 2 @C1 and C2] connected to the driving circuit [fig. 2 @T1] and the power input end [fig. 2 @ELVDD], wherein
the compensation circuit [fig. 2 @C1 and C2] is configured to provide a compensation path [¶0077, “During the above-mentioned second period t2, the turn-on condition changes to the turned off condition when the voltage between the gate and the source is equal to the threshold voltage of the first transistor T1 while the voltage of the source electrode drops when the first transistor T1 is kept in the floating state (source voltage Vs). At this time, the threshold voltage of the first transistor t1 is stored in the first capacitor C1”] for a turn-on threshold voltage of the driving transistor [threshold voltage Vth of T1];
a switch circuit [fig. 2 @T2-T4] connected to the driving circuit [fig. 2 @T1] and the compensation circuit [fig. 2 @C1 and C2], wherein
the switch circuit [fig. 2 @T2-T4] is configured to control [operation of T2-T4 controls current flow to and from the compensation circuit and the voltages stored in the compensation circuit] connections of the driving transistor [fig. 2 @T1] with the compensation circuit [fig. 2 @C1 and C2],
the data signal input end [fig. 2 @N1] and the power input end [fig. 2 @N2], to provide each pole of the driving transistor [figs. 2 and 3 @Vg and Vs and Vd] with different potentials for controlling the pixel circuit to be in different working phases [fig. 3 illustrates the different potentials on N1 and N2 during the t1-t4, fig. 2 illustrates T4 controlling Vd by setting Vd equal to ELVSS (¶0062)]; wherein the pixel circuit is configured to:
be at least in a discharge phase [fig. 3 @t2] before the light-emitting circuit in the pixel circuit is controlled to be in a light-emitting state [¶0091, “After the scanning period t1-t3 is completed, during the fourth period t4 set as the light emitting period”];
in the discharge phase [fig. 3 @t2], the source voltage [figs. 2 and 3 @N2/Vs] of the driving transistor [fig. 2 @T1] is discharged through the compensation circuit [construed as Vs charging C1 and C2] to compensate a threshold voltage of the driving transistor [¶0077, “During the … second period t2, the turn-on condition changes to the turned off condition when the voltage between the gate and the source is equal to the threshold voltage of the first transistor T1 while the voltage of the source electrode drops when the first transistor T1 is kept in the floating state (source voltage Vs). At this time, the threshold voltage of the first transistor t1 is stored in the first capacitor C1”]; wherein
the switch circuit [fig. 5 @T2-T5] comprises a first transistor [T2], a second transistor [fig. 5 @T3], a third transistor [fig. 5 @T4] and a fourth transistor [fig. 5 @T5],
the light-emitting circuit comprises a light-emitting diode [fig. 5 @OLED],
wherein: a gate of the driving transistor [fig. 5 @Vg] is connected to the data signal [fig. 5 @Dm] input end of the pixel circuit through a drain of the first transistor [fig. 5 @T2] and a source of the first transistor [fig. 5 @T2];
a source of the driving transistor [fig. 5 @T1] is connected to the power input [fig. 5 @ELVDD] end through a drain of the second transistor [fig. 5 @T3] and a source of the second transistor [fig. 5 @T3] in turn; and
a drain of the driving transistor [fig. 5 @T1] is connected to an anode of the light-emitting diode [fig. 5 @OLED] through a source of the fourth transistor [fig. 5 @T5] and a drain of the fourth transistor [fig. 5 @T5] in turn;
a gate of the first transistor [fig. 5 @T2] is configured to obtain a first control signal [fig. 5 @Sn], and
the first control signal is used for controlling turned-on and turned-off of the first transistor [¶0057, “the gate electrode of the second transistor T2 is connected to the scanning line Sn”];
a gate of the second transistor [fig. 5 @T3] and a gate of the fourth transistor [fig. 5 @T5] are configured to obtain a second control signal [fig. 5 @En], and
the second control signal [fig. 5 @En] is used for controlling turned-on and turned-off of the second transistor [fig. 5 @T3] and the fourth transistor [fig. 5 @T5];
a source of the third transistor [fig. 5 @T4] is connected to the drain of the driving transistor [fig. 5 @T1], a drain of the third transistor is grounded [fig. 5 @ ELVSS], a gate of the third transistor [fig. 5 @T4] is configured to obtain a third control signal [fig. 5 @ CSn], and the third control signal [fig. 5 @ CSn] is used for controlling turned-on and turned-off of the third transistor [ fig. 5 @T4]; wherein
the pixel circuit is configured to be controlled to enter a third phase [fig. 6 @t3-t4] through the switch circuit after the discharge phase [fig. 6 @t2];
in the third phase, the data signal input end provides a first data signal [fig. 6 @Vdata], and
an amplitude of the first data signal [fig. 6 @Vdata] is less than an amplitude of signal provided by the data signal input end in the discharge phase [fig. 6 @Vsus];
a gate of the driving transistor [fig. 6 @N1] obtains the first data signal [fig. 6 @Vdata] through the switch circuit [fig. 6 illustrates Sn opens T2 and provides Vdata to N1],
the substrate of the driving transistor is connected [Qian teaches driving transistor substrate is connected to source electrode of driving transistor] to the compensation circuit [fig. 5 @C1 and C2] through a source of the driving transistor [fig. 6 @Vs/N2], and
a drain of the driving transistor [fig. 5 @T1] is suspended [fig. 6 @CSn turns T4 off which terminates current flow from T1 to ELVSS through T4]
Jeong does not teach the driving transistor source voltage includes a substrate bias voltage
Qian teaches a driving transistor source voltage [fig. 1 @S] includes a substrate bias voltage [voltage on the transistor substrate (fig. 1 @100) is directly connected to source electrode of the driving transistor (fig. 1 @M2), fig. 1 teaches body connection electrode is directly connected to the transistor source electrode, page 8 lines 28-30, “the first connection electrode 111 is connected to the substrate terminal 103 through a via hole 131”]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of directly connecting the transistor source electrode and the transistor substrate, as taught by Qian, into the pixel circuit taught by Jeong in order that the high power supply terminal ELVDD will mitigate the change in driving transistor threshold voltage under the influence of external factors and will thereby improve the display quality (Qian: page 10 lines 12-17).
Regarding Claim 3 (Currently Amended), Jeong in view of Qian teaches the pixel circuit according to Claim 1, wherein
the first control signal [fig. 5 @Sn], the second control signal [fig. 5 @En] and the third control signal [fig. 5 @ CSn] at least provide a turned-on signal and a turned-off signal respectively to control the first transistor, the second transistor, the third transistor and the fourth transistor to be respectively in a corresponding turned-on state and a corresponding turned-off state [figs 5 and 6 teach the claimed control signal functionality].
Regarding Claim 4 (Original), Jeong in view of Qian teaches the pixel circuit according to Claim 1, wherein
the compensation circuit comprises a first capacitor [fig. 5 @C1] and a second capacitor [fig. 5 @C2],
the first capacitor and the second capacitor are sequentially connected in series between a gate of the driving transistor [fig. 5 @T1] and the power input end {ELVDD], and
an intermediate connection point [fig. 5 @N2/Vs] of the first capacitor and the second capacitor is connected to the substrate of the driving transistor through a source of the driving transistor [Qian: fig. 1 @M1 illustrates claimed connection].
Regarding Claim 5 (Original), Jeong in view of Qian teaches the pixel circuit according to Claim 1, wherein
the pixel circuit is configured to be controlled to enter an initial phase through the switch circuit [fig. 3 @Sn (turns on T2 and T4)];
in the initial phase [fig. 3 @t1], a voltage of a gate of the driving transistor [fig. 3 @Vg] rises to a first preset voltage [fig. 3 @Vsus], and
a voltage difference of the gate and a source of the driving transistor satisfies a turned-on condition of the driving transistor [¶0074].
Regarding Claim 6 (Original), Jeong in view of Qian teaches the pixel circuit according to Claim 3, wherein
the pixel circuit is configured to be controlled to enter the initial phase [through the switch circuit, by: controlling the first control signal [fig. 5 @Sn], the second control signal [fig. 5 @En] and the third control signal [fig. 5 @CSn] to provide the turned-on signal to control the first transistor [fig. 5 @T2], the second transistor [fig. 5 @T3], the third transistor [fig. 5 @T4] and the fourth transistor [fig. 5 @T5] to be in a turned-on state [fig. 6 illustrates all three control signals providing a turn-on signal to their respective transistor during t1], and
controlling the data signal input end to provide an initial voltage [fig. 6 @Vsus], thereby providing the first preset voltage to the gate of the driving transistor [T2 opens and provides Asus to Vg], so that the voltage difference of the gate and the source of the driving transistor [T1] satisfies the turned-on condition [¶0074, “The first voltage (Vsus) is set to a voltage lower than the first power supply (ELVDD) which is higher than the threshold voltage of the first transistor T1, thus the first transistor T1 is turned on”],
the source of the driving transistor [fig. 5 @T1] is connected to the power input end [fig. 5 @ELVDD] and the compensation circuit [fig. 5 @C1 and C2],
the drain of the driving transistor [fig. 5 @Vd] is connected to the light-emitting circuit [fig. 5 @OLED] through the fourth transistor [fig. 5 @T5] and is grounded [fig. 5 @ELVSS] through the third transistor [fig. 5 @T4].
Regarding Claim 7 (Original) Jeong in view of Qian teaches the pixel circuit according to Claim 5, wherein
during initial power-on [fig. 6 @ before t1], the pixel circuit is controlled to enter the initial phase [fig. 6 @t1] until the voltage of the gate of the driving transistor [fig. 6 @N1] reaches the first preset voltage [fig. 6 @Vsus], and
the voltage difference of the gate [N1] and the source of the driving transistor [N2] satisfies the turned-on condition of the driving transistor [¶0074, “The first voltage (Vsus) is set to a voltage lower than the first power supply (ELVDD) which is higher than the threshold voltage of the first transistor T1, thus the first transistor T1 is turned on”].
Regarding Claim 8 (Currently Amended), Jeong in view of Qian teaches the pixel circuit according to Claim 1, wherein
the pixel circuit is configured to be controlled to enter the discharge phase [fig. 6 @before t2] through the switch circuit [fig. 6 @En controls T3 off];
in the discharge phase [fig. 6 @t2], the substrate of the driving transistor [N2/Vs] is discharged to the compensation circuit [fig. 6 @N2 decreases to charge C1 with Vth] through a source of the driving transistor [Qian teaches the substrate of the driving transistor is directly connected to the source electrode], and
a voltage difference of a gate [N1] and the source [N2] of the driving transistor [T1] changes until the driving transistor is in a turned-off state [¶0077, “During the above-mentioned second period t2, the turn-on condition changes to the turned off condition when the voltage between the gate and the source is equal to the threshold voltage of the first transistor T1”].
Regarding Claim 9 (Original), Jeong in view of Qian teaches the pixel circuit according to Claim 8, wherein the pixel circuit is configured to be controlled to enter the discharge phase through the switch circuit, by:
controlling the second control signal [fig. 6 @En] to provide a turned-off signal, the first control signal [fig. 6 @Sn] and the third control signal [fig. 6 @CSn] to provide a turned-on signal, to control the first transistor [T2] and third transistor [T4] to be turned on, and the second transistor [T3] and fourth transistor [T5] to be turned off [fig. 6 illustrates claimed switch operations], and
controlling the data signal input end to provide an initial voltage [fig. 6 @Vsus]; wherein
the initial voltage is used for making the driving transistor in a turned-on state in an initial phase [¶0074, “The first voltage (Vsus) is set to a voltage lower than the first power supply (ELVDD) which is higher than the threshold voltage of the first transistor T1, thus the first transistor T1 is turned on”];
the substrate of the driving transistor [Qian teaches driving transistor substrate directly connected to Vs/N2] is connected to the compensation circuit through the source [fig. 6 @Vs/N2] of the driving transistor, and
is discharged to the compensation circuit [during t2 C1 is charged to Vth by discharging Vs /N2 which Qian teaches includes the substrate voltage].
Regarding Claim 10 (Original), Jeong in view of Qian teaches the pixel circuit according to Claim 5, wherein
in the initial phase [fig. 6 @t1], after the driving transistor is turned on, the pixel circuit is controlled to enter the discharge phase [fig. 6 after t1, En causes start of t2], and
the discharge phase continues until the driving transistor is turned off [¶0077, “During the above-mentioned second period t2, the turn-on condition changes to the turned off condition when the voltage between the gate and the source is equal to the threshold voltage of the first transistor T1”].
Regarding Claim 12 (Currently Amended), Jeong in view of Qian teaches the pixel circuit according to Claim 1, wherein
the pixel circuit is controlled to enter the third phase [fig. 6 @t3-t4] through the switch circuit, by:
controlling the first control signal [fig. 6 @Sn] to provide a turned-on signal to control the first transistor to be turned on [at t3 Sn turns T2 on], and
controlling a second control signal [fig. 6 @En] and a third control signal [fig. 6 @ESn] to provide a turned-off signal [fig. 6 @En provides off signal before t4, fig. 6 @ CSn provides turn off signal before t3-t4] to control the second transistor [fig. 6 @T3], the third transistor [fig. 5 @T4] and the fourth transistor [fig. 5 @T5] to be turned off.
Regarding Claim 13 (Currently Amended), Jeong in view of Qian teaches the pixel circuit according to Claim 1, wherein
the pixel circuit is configured to be controlled to enter a light-emitting phase [fig. 6 @t4] through the switch circuit after the third phase [fig. 6 @t3-t4];
in the light-emitting phase, the gate of the driving transistor [fig. 6 @N1] obtains a turned-on voltage and is in the turned-on state [fig. 6 illustrates Sn turns T2 on before t4];
a source of the driving transistor [fig. 6 @Vs/N2] is connected to the power input end [fig. 5 @ELVDD] and the compensation circuit, and the drain of the driving transistor [fig. 5 @Vd] is connected [fig. 6 illustrates En turns T3 and T4 on before t4] to the light-emitting circuit [fig. 5 @OLED] through a source and a drain of a fourth transistor [fig. 5 @T5].
Regarding Claim 14 (Original), Jeong in view of Qian teaches the pixel circuit according to Claim 13, wherein
the pixel circuit is controlled to enter the light-emitting phase [fig. 6 @t4] through the switch circuit, by:
controlling the second control signal [fig. 6 @En] to provide a turned-on signal [fig. 6 @t4],
controlling the first control signal [fig. 6 @Sn] and the third control signal [fig. 6 @SCn] to provide a turned-off signal to control the second transistor [T3] and the fourth transistor [T5] to be turned on [fig. 6 illustrates claimed states], and
the first transistor [T2] and the third transistor [T4] to be turned off [fig. 6 illustrates claimed states].
Regarding Claim 15 (Original), Jeong in view of Qian teaches the pixel circuit according to Claim 13, wherein
the pixel circuit controls the light-emitting circuit to be in a light-emitting state during the light-emitting phase [fig. 6 @t4];
before entering the light-emitting phase [fig. 6 @t4], the pixel circuit is sequentially controlled to enter the initial phase [fig. 6 @t1] and the discharge phase [fig. 6 @t2] to control the driving transistor [T1] to be turned on [¶0074, “The first voltage (Vsus) is set to a voltage lower than the first power supply (ELVDD) which is higher than the threshold voltage of the first transistor T1, thus the first transistor T1 is turned on”], and
after the driving transistor is turned on, the threshold voltage difference caused by the substrate bias voltage [Qian teaches T1 substrate connected to Vs/N2 and the substrate voltage is indistinguishable from Vs/N2 during discharge phase t2] of the driving transistor is compensated [¶0077, “During period t2, the turn-on condition changes to the turned off condition when the voltage between the gate and the source is equal to the threshold voltage of the first transistor T1 while the voltage of the source electrode drops … the threshold voltage of the first transistor t1 is stored in the first capacitor C1”].
Regarding Claim 17 (Original), Jeong in view of Qian teaches the control method of the pixel circuit according to Claim 16, wherein
before controlling the light-emitting circuit in the pixel circuit to be in the light-emitting state [fig. 6 @t4], the control method further comprises:
controlling the driving transistor to be turned on through the switch circuit [¶0076, “In addition, the second and fourth transistor T2, T4 are kept on the turn-on condition by the scanning signal of low voltage, and then the gate voltage Vg and the drain voltage Vd of the first transistor T1 are the first voltage (Vsus) and the voltage of the second power supply (ELVSS), respectively”];
after the driving transistor is turned on [¶0073, “the first transistor T1 is initialized while the first voltage (Vsus), the voltage of the first power supply (ELVDD) and the voltage of the second power supply (ELVSS) are delivered to the gate electrode, the source electrode and the drain electrode of the first transistor T1 during the first period t”, ¶0074, “The first voltage (Vsus) is set to a voltage lower than the first power supply (ELVDD) which is higher than the threshold voltage of the first transistor T1, thus the first transistor T1 is turned on”],
controlling the substrate of the driving transistor [Qian teaches directly connecting driving transistor source and driving transistor substrate so that Vs reflects the substrate bias and threshold voltage] to discharge to the compensation circuit [fig. 6 illustrates source voltage discharging through T1 and compensation circuit (charging C1 and C2 is equivalent to discharging Vs)], thereby
compensating the threshold voltage difference caused by the substrate bias voltage of the driving transistor [Vs is reduced from ELVDD to Vsus +Vth while Vg is Vsus, reduction includes removal of any driving transistor substrate voltage until the difference between N1 and N2 is Vth which is stored in capacitor C1] .
Regarding Claim 18 (Original), Jeong in view of Qian teaches the control method of the pixel circuit according to Claim 16, wherein
the controlling the driving transistor to be turned on through the switch circuit, comprises: controlling a voltage of a gate of the driving transistor to rise to a first preset voltage through the switch circuit [fig. 5 @Sn opens fig. 5 @T2 which applies Vsus to node N1 which is also Vg], and
controlling a voltage difference of the gate and a source of the driving transistor to satisfy a turned-on condition of the driving transistor [¶0074, “The first voltage (Vsus) is set to a voltage lower than the first power supply (ELVDD) which is higher than the threshold voltage of the first transistor T1, thus the first transistor T1 is turned on”].
Regarding Claim 19 (Original), Jeong in view of Qian teaches the control method of the pixel circuit according to Claim 16, wherein the controlling the substrate of the driving transistor to discharge to the compensation circuit, comprises:
controlling by the switch circuit, the substrate of the driving transistor to be connected [fig. 6 @En turns T3 off causing discharge of Vs/N2 and charging of C1] to the compensation circuit [fig. 5 @C1 and C2] through a source [Qian teaches driving transistor substrate shorted to Vs/N2] of the driving transistor [fig. 5 @Vs/N2],
controlling the control circuit to discharge to the compensation circuit [charge on C1 decreases from N2-N1 of ELVDD -Vsus to Vsus -Vsus+Vth], and
controlling a voltage difference of a gate and the source of the driving transistor to be changed until the driving transistor is turned off [¶0077, “During the above-mentioned second period t2, the turn-on condition changes to the turned off condition when the voltage between the gate and the source is equal to the threshold voltage of the first transistor T1”].
.
Regarding Claim 20 (Original), Jeong in view of Qian teaches the control method of the pixel circuit according to Claim 16, wherein
after the at least controlling the pixel circuit to be in the discharge phase [fig. 6 @t2], the control method further comprises:
providing, by the data signal input end, a first data signal [fig. 6 illustrates Vdata provided after t2], wherein
an amplitude of the first data signal [fig. 6 illustrates Vsus larger than Vdata] is less than an amplitude of a signal provided by the data signal input end in the discharge phase;
controlling, a transistor of the switch circuit between a gate of the driving transistor and the data signal input end to be turned on [fig. 6 illustrates Sn turns T2 on after t2 applying Vdata to N1],
controlling the substrate of the driving transistor to be connected [Qian teaches driving transistor substrate is connected to source electrode of driving transistor] to the compensation circuit [fig. 5 illustrates Vs/N2 connected to C1 and C2] through a source of the driving transistor, and
controlling a drain [Vd] of the driving transistor [fig. 5 @T1] to be suspended [fig. 6 @CSn turns T4 off which terminates current flow from T1 to ELVSS through T4].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The Examiner can normally be reached 1000-1800 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Douglas Wilson/Primary Examiner, Art Unit 2622
Prosecution Insights