Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 5 August 2026.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
controller in claim 1, support for which was taken as FIG 2: 125 and [0047]
transfer logic in claim 1, support for which was taken as FIG 2: 127 and [0047]
data transfer device in claim 15, support for which was taken as FIG 2: 124 and [0047]
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanuri (US PG PUB No. 20090037689) in view of Bavishi (US PG PUB No. 20210157520).
As per claim 1, a data transfer device (see Kanuri FIG 2: 120) comprising:
a controller (see Kanuri FIG 2: 220) configured to:
receive a data transfer request from a processor (see Kanuri FIG 4: 410 and [0055]: “In step 410, storage controller 120 receives a request to transfer a desired sequence of data elements from a storage device to a main memory”); and
responsive to the data transfer request, obtain data from a source memory location and transfer the data to a destination memory location (see Kanuri [0055]: “In step 410, storage controller 120 receives a request to transfer a desired sequence of data elements from a storage device to a main memory, with the request specifying where location descriptors are located.”); and
[The storage device and the main memory are taken as the respective source and destination as recited in the claims.]
transfer logic configured to optimize the transfer of the data from the source memory location to the destination memory location by performing at least one data transfer operation (see Kanuri [0083]: “Thus, bus master 250 may initiate DMA transfer of the corresponding portions to main memory 130 as soon as the portions (or at least a minimum portion allowed to be transferred in a DMA transfer) are available.”).
However, Kanuri does not expressly disclose but in the same field of endeavor Bavishi discloses
wherein the at least one data transfer operation comprises manipulating the data or rearranging data elements of the data to generate transformed data that is transferred to the destination memory location (see Bavishi FIG 4: 420, 440 and [0044]).
It would have been obvious before the effective filing date of the invention to further generate transformed data as taught by Bavishi.
The suggestion/motivation for doing so would have been for the benefit optimizing data transfer between source and destination memory locations having different characteristics (see Bavishi [0042]).
Therefore it would have bene obvious before the effective filing date of the invention to modify Kanuri to further generate transformed data as taught by Bavishi for the benefit of optimizing transfer between source and destination memory locations having different characteristics to arrive at the invention as specified in the claims.
As per claim 2, the data transfer device of claim 1,
wherein the data transfer device obtains the data, performs the at least one data transfer operation on the data, and transfers the data to the destination memory location independently of the processor (see Kanuri [0083]: “DMA”).
As per claim 3, the data transfer device of claim 1,
wherein controller is further configured to notify the processor that the transfer is complete after an optimized transfer of the data to the destination memory location (see Kanuri [0041]: “When the last data element is stored, bus master 250 may first send an interrupt to CPU 110 (indicating that the data transfer is complete) and relinquish control of bus 112.”).
As per claim 4, the data transfer device of claim 1,
wherein the source memory location and the destination memory location are in different types of memory (see Kanuri [0055]).
As per claim 5, the data transfer device of claim 1,
wherein the data transfer request identifies the source memory location, the destination memory location, and a size of the data (see Kanuri [0047]).
As per claim 6, the data transfer device of claim 1,
wherein the at least one data transfer operation comprises rearranging data elements of the data to generate transformed data (see Kanuri [0028]: “data related to multiple requests may re-ordered (during reception), but the data related to each request may continue to be received in the same order as in which the data is (logically) stored in the secondary storage.”).
As per claim 7, the data transfer device of claim 1,
wherein the at least one data transfer operation comprises manipulating the data to generate transformed data.
As per claim 8, the data transfer device of claim 1,
wherein the data transfer request specifies a source address to destination address mapping function (see Kanuri [0042]).
[The location descriptor is taken as a mapping function.]
As per claim 9, the data transfer device of claim 8,
wherein the at least one data transfer operation comprises controlling an access order to obtain the data from the source address or transfer the data to the destination based on the mapping function (see Kanuri [0028]: “data related to multiple requests may re-ordered (during reception), but the data related to each request may continue to be received in the same order as in which the data is (logically) stored in the secondary storage.”).
As per claim 10, the data transfer device of claim 9,
wherein the access order is modified to optimize for memory architecture characteristics of the source memory location and the destination memory location (see Kanuri [0028]: “data related to multiple requests may re-ordered (during reception), but the data related to each request may continue to be received in the same order as in which the data is (logically) stored in the secondary storage.”).
As per claim 11, the data transfer device of claim 1,
further comprising at least one intermediate storage buffer configured to temporarily store data during the at least one data transfer operation (see Kanuri FIG 2: 210 and [0038]).
As per claim 12, the data transfer device of claim 1,
further comprising source address generation logic (see Kanuri FIG 1: 130), intermediate address generation logic (see Kanuri FIG 1: 120), and destination address generation logic (see Kanuri FIG 1: 140A).
[Each of the Main Memory, the Storage Controller, and The Secondary Storage Unit necessarily comprise address generation logic to access the respective storage.]
As per claim 13, the data transfer device of claim 1,
wherein the transfer logic is coupled to the controller (see Kanuri FIG 2: 210 and [0038]).
As per claim 14, the data transfer device of claim 1,
wherein the transfer logic is implemented as a part of the controller (see Kanuri FIG 2: 120 and [0035]).
As per claim 15, a system comprising:
a processor (see Kanuri FIG 1:110);
memory comprising a first memory space (see Kanuri FIG 1: 130) and a second memory space (see Kanuri FIG 1: 140A), the second memory space being heterogeneous to the first memory space (see Kanuri [0055]); and
a data transfer device configured to:
receive a data transfer request from the processor (see Kanuri FIG 4: 410 and [0055]: “In step 410, storage controller 120 receives a request to transfer a desired sequence of data elements from a storage device to a main memory”);
responsive to the data transfer request, obtain data from a first memory location in the first memory space location (see Kanuri [0055]: “In step 410, storage controller 120 receives a request to transfer a desired sequence of data elements from a storage device to a main memory, with the request specifying where location descriptors are located.”);
transfer the data from the first memory location to a second memory location in the second memory space (see Kanuri [0083]: “Thus, bus master 250 may initiate DMA transfer of the corresponding portions to main memory 130 as soon as the portions (or at least a minimum portion allowed to be transferred in a DMA transfer) are available.”); and
optimize the transfer of the data from the first memory location to the second memory location by performing at least one data transfer operation (see Kanuri [0083]).
However, Kanuri does not expressly disclose but in the same field of endeavor Bavishi discloses
wherein the at least one data transfer operation comprises manipulating the data or rearranging data elements of the data to generate transformed data that is transferred to the destination memory location (see Bavishi FIG 4: 420, 440 and [0044]).
It would have been obvious before the effective filing date of the invention to further generate transformed data as taught by Bavishi.
The suggestion/motivation for doing so would have been for the benefit optimizing data transfer between source and destination memory locations having different characteristics (see Bavishi [0042]).
Therefore it would have bene obvious before the effective filing date of the invention to modify Kanuri to further generate transformed data as taught by Bavishi for the benefit of optimizing transfer between source and destination memory locations having different characteristics to arrive at the invention as specified in the claims.
As per claim 16, the system of claim 15,
wherein the first memory space and the second memory space are implemented using different physical memory systems (see Kanuri [0055]: “In step 410, storage controller 120 receives a request to transfer a desired sequence of data elements from a storage device to a main memory, with the request specifying where location descriptors are located.”).
As per claim 17, the system of claim 15,
wherein the first memory space and the second memory space are implemented at a same physical memory module (see Bavishi [0019]).
As per claim 18, a method comprising:
receive, by a data transfer device, a data transfer request from a processor (see Kanuri FIG 4: 410 and [0055]: “In step 410, storage controller 120 receives a request to transfer a desired sequence of data elements from a storage device to a main memory”);
responsive to the data transfer request, obtain, by the data transfer device, data from a source memory location (see Kanuri [0055]: “In step 410, storage controller 120 receives a request to transfer a desired sequence of data elements from a storage device to a main memory, with the request specifying where location descriptors are located.”);
temporarily store, by the data transfer device, the data during at least one data transfer operation performed by the data transfer device to optimize transfer of the data between the source memory location and a destination memory location (see Kanuri [0083]: “Thus, bus master 250 may initiate DMA transfer of the corresponding portions to main memory 130 as soon as the portions (or at least a minimum portion allowed to be transferred in a DMA transfer) are available.”); and
transfer, by the data transfer device, the data to the destination memory location (see Kanuri [0083]).
However, Kanuri does not expressly disclose but in the same field of endeavor Bavishi discloses
wherein the at least one data transfer operation comprises manipulating the data or rearranging data elements of the data to generate transformed data that is transferred to the destination memory location (see Bavishi FIG 4: 420, 440 and [0044]).
It would have been obvious before the effective filing date of the invention to further generate transformed data as taught by Bavishi.
The suggestion/motivation for doing so would have been for the benefit optimizing data transfer between source and destination memory locations having different characteristics (see Bavishi [0042]).
Therefore it would have bene obvious before the effective filing date of the invention to modify Kanuri to further generate transformed data as taught by Bavishi for the benefit of optimizing transfer between source and destination memory locations having different characteristics to arrive at the invention as specified in the claims.
As per claim 19, the method of claim 18, further comprising:
generating, by the data transfer device, a mapping function for converting source addresses to destination addresses (see Kanuri [0042]) ; and
[The location descriptor is taken as a mapping function.]
modifying, by the data transfer device, an access order for obtaining the data from the source memory location or transforming the data for transfer to the destination memory location based on the mapping function (see Kanuri [0028]: “data related to multiple requests may re-ordered (during reception), but the data related to each request may continue to be received in the same order as in which the data is (logically) stored in the secondary storage.”).
As per claim 20, the method of claim 19 wherein transforming the data for transfer comprises at least one of:
rearranging the data elements of the obtained data to generate the transformed data (see Kanuri [0028]: “data related to multiple requests may re-ordered (during reception), but the data related to each request may continue to be received in the same order as in which the data is (logically) stored in the secondary storage.”); and
converting the obtained data from a first data type to a second data type (see Bavishi FIG 4: 420, 440 and [0044]).
RESPONSE TO ARGUMENTS
The rejection of claims 15-17 under 35 USC 112(b) is withdrawn in view of the Amendments and Applicant’s arguments.
1st ARGUMENT:
The Office relies on Kanuri paragraph [0083] for the transfer-logic feature of claim 1. This section of Kanuri describes that "bus master 250 may initiate DMA transfer of the corresponding portions to main memory 130 as soon as the portions (or at least a minimum portion allowed to be transferred in a DMA transfer) are available." Kanuri is a storage controller that transfers a requested sequence of data elements from secondary storage to main memory unchanged. As Kanuri paragraph [0028] explains, "the data related to each request may continue to be received in the same order as in which the data is (logically) stored in the secondary storage." Merely moving the data via DMA is not the same as "manipulating the data or rearranging data elements of the data to generate transformed data that is transferred to the destination memory location," as recited in amended claim 1. This subject matter is simply missing from Kanuri.
Examiner notes Bavishi is relied upon to teach the argued subject matter.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
