DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hong, US Patent Publication 2023/0105266.
Regarding independent claim 1, Hong teaches a gate driver, comprising:
a plurality of signal transmission circuits (ST(x) of figure 1 as given in paragraph 0045) that are dependently connected via carry lines (Cout(x) of figure 1 as given paragraph 0048), wherein each of the plurality of signal transmission circuits is connected to a respective carry line to which a respective carry signal is applied from a respective previous signal transmission circuit (paragraph 0048 explains “the other signal transmission units, ST(n−1), ST(n), ST(n+1), and ST(n+2) respectively receive the carry signals Cout(n−2), Cout(n−1), Cout(n), and Cout(n+1) from the previous signal transmission unit and start to be driven” and paragraph 0082 explains how each circuit “may receive a carry signal from a previous signal transmission unit to charge or discharge voltages of the first control node and the second control node”), and wherein each of the plurality of signal transmission circuits is configured to output a respective gate signal in response to a respective clock signal (paragraph 0049 explains the output of gate signals of scan pulses SCOUT(x) based on the shift clock CLKx as given in paragraph 0048);
wherein an (n)th signal transmission circuit, where n is a positive integer, includes:
an output circuit configured to receive an (n-1)th carry signal from a previous signal transmission circuit, an (n+1)th carry signal from a next signal transmission circuit, and a clock signal (figure 1 shows that each signal transmission circuit ST(x) has the carry signals of the other circuits of Cout(x-1) and Cout(x+1) and clock CLK and paragraph 0054 explains how the carry signal from the previous signal transmission unit is used and paragraph 0058 explains how the carry signal from the next signal transmission unit is used), and to charge or discharge a first control node and a second control node to output a gate signal (paragraph 0052 explains how the circuits are used to charge and discharge the nodes to output the gate signal of SCOUT(x) as depicted in figure 2); and
a selection circuit configured to selectively charge the first control node so that the gate signal is output from the output circuit connected to a predetermined gate line among predetermined gate lines (paragraphs 0055 and 0068 explains how node Q is charged and the output scan pulse SCOUT(x) is output based on the potential of the Q node), and
wherein the clock signal is modulated such that the clock signal is supplied to the signal transmission circuits corresponding to a selected region during a period in which gate signals are output to gate lines disposed in the selected region (paragraphs 0044, 0048, and 0087 explain the synchronization of the clock and gate signals in a given frame and how the shifted signals are applied for the different regions).
Although all of the features are taught by Hong, they are spread out over different embodiments. It would have been obvious to one of ordinary skill before the effective filing date to combine the features of the gate drivers of the different embodiments as explained above. The rationale to combine would be to make modifications and variations without departing from the technical idea or scope of the disclosure (paragraph 0164 of Hong).
Regarding independent claim 10, Hong teaches a display device (depicted in figure 11 and given in paragraphs 0122-0123), comprising:
a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged (figure 11 depicts the pixel array AA described in paragraph 0124 with data lines 102 and gate lines 103 as given in paragraphs 0123-0124 and pixels 101 as given in paragraphs 0127-0128);
a data driver (data driver 110 of figure 11 as given in paragraph 138) configured to output data voltages to the plurality of data lines (as described in paragraphs 0139 and 0142);
a gate driver (gate driver 120 of figure 11 as given in paragraph 138) configured to output gate signals to the plurality of gate lines (as described in paragraph 0143); and
a timing controller (timing controller 130 of figure 11 as given in paragraphs 0089 and 0142) configured to control a timing operation of the data driver and the gate driver (as given in paragraph 0089),
wherein the gate driver comprises:
a plurality of signal transmission circuits (ST(x) of figure 1 as given in paragraph 0045) that are dependently connected via carry lines (Cout(x) of figure 1 as given paragraph 0048), wherein each of the plurality of signal transmission circuits is connected to a respective carry line to which a respective carry signal is applied from a respective previous signal transmission circuit (paragraph 0048 explains “the other signal transmission units, ST(n−1), ST(n), ST(n+1), and ST(n+2) respectively receive the carry signals Cout(n−2), Cout(n−1), Cout(n), and Cout(n+1) from the previous signal transmission unit and start to be driven” and paragraph 0082 explains how each circuit “may receive a carry signal from a previous signal transmission unit to charge or discharge voltages of the first control node and the second control node”), and wherein each of the plurality of signal transmission circuits is configured to output a respective gate signal in response to a respective clock signal (paragraph 0049 explains the output of gate signals of scan pulses SCOUT(x) based on the shift clock CLKx as given in paragraph 0048); and
wherein an (n)th signal transmission circuit, where n is a positive integer, includes:
an output circuit configured to receive an (n-1)th carry signal from a previous signal transmission circuit, an (n+1)th carry signal from a next signal transmission circuit, and a clock signal (figure 1 shows that each signal transmission circuit ST(x) has the carry signals of the other circuits of Cout(x-1) and Cout(x+1) and clock CLK and paragraph 0054 explains how the carry signal from the previous signal transmission unit is used and paragraph 0058 explains how the carry signal from the next signal transmission unit is used), and to charge or discharge a first control node and a second control node to output a gate signal (paragraph 0052 explains how the circuits are used to charge and discharge the nodes to output the gate signal of SCOUT(x) as depicted in figure 2); and
a selection circuit configured to selectively charge the first control node so that the gate signal is output from the output circuit connected to a predetermined gate line among predetermined gate lines (paragraphs 0055 and 0068 explains how node Q is charged and the output scan pulse SCOUT(x) is output based on the potential of the Q node), and
wherein the clock signal is modulated such that the clock signal is supplied to the signal transmission circuits corresponding to a selected region during a period in which gate signals are output to gate lines disposed in the selected region (paragraphs 0044, 0048, and 0087 explain the synchronization of the clock and gate signals in a given frame and how the shifted signals are applied for the different regions).
Although all of the features are taught by Hong, they are spread out over different embodiments. It would have been obvious to one of ordinary skill before the effective filing date to combine the features of the gate drivers of the different embodiments as explained above. The rationale to combine would be to make modifications and variations without departing from the technical idea or scope of the disclosure (paragraph 0164 of Hong).
Allowable Subject Matter
Claims 2-7, 9, 11-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record, taken alone or in combination, teaches “the selection circuit [includes/comprises] a first transistor, a second transistor, a third transistor, and a fourth transistor; the first transistor [includes/comprises] a gate electrode to which a selection signal is applied, a first electrode to which the gate signal is applied, and a second electrode connected to a first node; the second transistor [includes/comprises] a gate electrode connected to the first node, a first electrode to which a start signal is applied, and a second electrode connected to a second node; the third transistor [includes/comprises] a gate electrode to which the start signal is applied, a first electrode connected to the second node, and a second electrode connected to the first control node; and the fourth transistor [includes/comprises] a gate electrode to which a reset signal is applied, a first electrode connected to the first control node, and a second electrode to which a low-potential voltage is applied” as given in claims 2 and 11 and “the output circuit comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the fifth transistor comprises a gate electrode and a first electrode to which the (n-1)th carry signal is applied, and a second electrode connected to the first control node; the sixth transistor comprises a gate electrode to which the (n+1)th carry signal is applied, a first electrode connected to the first control node, and a second electrode to which a low-potential voltage is applied; the seventh transistor comprises a gate electrode connected to the second control node, a first electrode connected to the first control node, and a second electrode to which the low-potential voltage is applied; the eighth transistor comprises a gate electrode and a first electrode to which a high-potential voltage is applied, and a second electrode connected to the second control node; the ninth transistor comprises a gate electrode connected to the first control node, a first electrode connected to the second control node, and a second electrode to which the low-potential voltage is applied; the tenth transistor comprises a gate electrode connected to the first control node, a first electrode to which the clock signal is applied, and a second electrode connected to an output node where the gate signal is output; and the eleventh transistor comprises a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode to which the low-potential voltage is applied” as given in claims 9 and 20. All other claims are objected to as being dependent on an allowable base claim.
Response to Arguments
Applicant's arguments filed 9/26/26 have been fully considered but they are not persuasive. Applicant contends that the prior art does not teach the amended features, rendering the claims to be allowable. The examiner disagrees. These features were not previously claimed and have now been appropriately rejected above.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., wherein the clock signal is modulated such that the clock signal is supplied to the signal transmission circuits corresponding to a selected region during a period in which gate signals are output to gate lines disposed in the selected region) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The closest prior art is made of record in the attached notice of references cited.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARUL H GUPTA whose telephone number is (571)272-5260. The examiner can normally be reached Monday through Friday, from 10 AM to 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PARUL H GUPTA/Primary Examiner, Art Unit 2627
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