DETAILED ACTION
This communication is in response to Application No. 19/096,513 originally filed 03/31/2025. The Request for Continued Examination and Amendment presented on 06/23/2026 which provides amendments to claims 1, 3, 11, 14 and claims 2, 12, 15 are cancelled is hereby acknowledged.
Currently claims 1, 3-11, 13-14, and 16-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/23/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-11, 13-14, and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 6-7, 9-16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi U.S. Patent Application Publication No. 2007/0139313 A1 hereinafter Choi in view of Lee et al. U.S. Patent Application Publication No. 2003/00858565 A1 hereinafter Lee in view of Nakajima et al. U.S. Patent Application Publication No. 2002/0135556 A1 hereinafter Nakajima in view of Koyama U.S. Patent Application Publication No. 2012/0062529 A1 hereinafter Koyama.
Consider Claim 1:
Choi discloses a display device comprising: (Choi, See Abstract.)
a display panel including a pixel connected to a data line, the display panel being configured to display an image; and (Choi, [0050], “The pixel unit 230 may receive a first power source ELVDD and a second power source ELVSS from an external source. The first power source ELVDD and the second power source ELVSS may be supplied to the pixel unit 230, and may be respectively supplied to the pixels 240. The pixels 240 receiving the first power source ELVDD and the second power source ELVSS may display images corresponding to data signals supplied from the data driving circuit 222.”)
a data driver configured to provide a data signal to the data line, wherein the data driver includes: (Choi, [0048] The data driver 220 may generate data signals in response to data driving control signals DCS from the timing controller 250. The data driver 220 may supply the generated data signals to the data lines D1 to Dm in sequence. The data driving circuit 222 may convert data supplied from an external source into data signals and supply the data signals to the data lines D1 to Dm. The data driving circuit 222 will be described in more detail below.”)
a shift register configured to generate a sampling signal; (Choi, [0053], “The shift register unit 223 may receive a source shift clock SSC and a source start pulse SSP from the timing controller 250. The shift register unit 223 receiving the source shift clock SSC and the source start pulse SSP may generate "i" sampling signals in sequence, while allowing the source start pulse SSP to be shifted depending on the source shift clock SSC. The shift register unit 223 may include "i" shift registers 2231 to 223i.”)
a sampling latch configured to latch image data in response to the sampling signal; (Choi, [0054], “The sampling latch unit 224 may store data in sequence depending on the sampling signals supplied in sequence from the shift register unit 223. The sampling latch unit 224 may include "i" sampling latches 2241 to 224i for storing "i" data. Each size of the sampling latches 2241 to 224i may be set to store k bit data. For the sake of discussion, this exemplary sampling latch unit 224 will be described assuming that k bit is 6 bits.”)
a holding latch configured to store an output of the sampling latch; (Choi, [0055], “The holding latch unit 225 may receive and store the data from the sampling latch unit 224 in response to a source output enable SOE signal. The holding latch unit 225 may supply the stored data to a level shifter 226. The holding latch unit 225 may include "i" holding latches 2251 to 225i. Each of the holding latches 2251 to 225i may be configured to store k bit data.”)
a decoder configured to convert an output of the holding latch into an analog signal; and (Choi, [0058], [0061], “FIG. 5 illustrates a block circuit diagram of an exemplary data signal generator as illustrated in FIGS. 4A and 4B. Referring to FIG. 5, the data signal generator 227 may include, for each channel, a first DAC 300, a second DAC 302 and a decoder unit 304.”)
a buffer configured to provide an output of the decoder to the data line. (Choi, [0060], “Referring to FIG. 4B, a buffer unit 228 may be connected between the data signal generator 227 and the data lines Dl to Di. The buffer unit 228 may supply the data signals supplied from the data signal generator 227 to the data lines D1 to Di.”)
wherein the first chip includes a low voltage element having a node level higher than a node level of a high voltage element integrated in the display panel, and does not include the high voltage element, and (Choi, [0062], “The first DAC 300 may receive the plurality of reference voltages (ref) from a gamma unit 229. The first DAC 300 may select a first reference voltage (ref1) and a second reference voltage (ref2) from the plurality of reference voltages (refs) depending on, e.g., a value of upper bits of the data. The first DAC 300 may receive the data from the level shifter 226, or directly from the holding latch unit 225, depending on the implementation.”)
Choi however does not specify wherein the sampling latch is integrated in a first chip different from the display panel, and wherein the buffer is integrated in the display panel.
Lee however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide wherein the sampling latch is integrated in a first chip different from the display panel, and wherein the buffer is integrated in the display panel. (Lee, [0108-0114], [0109], “The output buffer IC's 178A and 178B may be commonly connected in pairs of two to each of the TCP's 174 mounted with the DAC IC 176 in a liquid crystal display panel 180 by the CGO system. Each of the TCP's 174 may be electrically connected to the output buffer IC's 178A and 178B via pads provided at an upper portion of the liquid crystal display panel 180, and may be electrically connected to output pads provided at a data PCB 172. The data PCB 172 may transmit various control signals applied from the timing controller 110 and pixel data signals to the DAC IC's 176.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide portions of the data driver directly mounted on the display panel substrate as this was a known technique to those of skill in the art in view of Lee and would have been utilized for the purpose of reducing the number of components, preventing an increase in driving frequencies and reducing manufacturing costs. (Lee, [0110])
Choi in view of Lee however do not specify the arrangement of a first level shifter connected between the sampling latch and the holding latch and configured to covert a low voltage output from the sampling latch into a high voltage and to provide the high voltage to the holding latch.
Nakajima however teaches that it was a technique known to those having ordinary skill in the art before the effective filing date of the invention to provide a first level shifter connected between the sampling latch and the holding latch and configured to covert a low voltage output from the sampling latch into a high voltage and to provide the high voltage to the holding latch. (Nakajima, [0107], “Specifically, in the first and second horizontal driving systems 62, 63, level shift circuits 625, 635 and latch circuits 626, 636 for the H start pulse are provided and level shift circuit groups 627, 637 for the H clock pulse are provided corresponding to the respective shift stages. Moreover, level shift circuit groups 628, 638 for the display data are provided corresponding to the respective latch stages of the sampling and first latch circuits 622, 632. In the vertical driving system 64, only a level shift circuit 642 for the V start pulse and the V clock pulse is provided.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide level shifter connected between the sampling latch and the holding latch as this was a known technique in view of Nakajima and would have been utilized for the purpose of driving schemes that allow reduction in power consumption can be realized. (Nakajima, [0126])
Choi in view of Lee in view of Nakajima while teaching the arrangement however do not appear to provide details of the transistor themselves wherein the low voltage element has a transistor size and a circuit distance, which are smaller than a transistor size and a circuit distance of the high voltage element.
Koyama however teaches that it was known technique wherein the low voltage element has a transistor size and a circuit distance, (Koyama, [0221], “FIGS. 21A to 21C show the gate voltage V.sub.g dependence of the drain current I.sub.d (a solid line) and the mobility .mu. (a dotted line) of the transistor having the structure illustrated in FIG. 23B where the offset length L.sub.off is 5 nm. The drain current I.sub.d is obtained by calculation under the assumption that the drain voltage is +1 V and the mobility .mu. is obtained by calculation under the assumption that the drain voltage is +0.1 V. FIG. 21A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating layer is 15 nm, FIG. 21B shows that of the transistor in the case where the thickness of the gate insulating layer is 10 nm, and FIG. 21C shows that of the transistor in the case where the thickness of the gate insulating layer is 5 nm.”)
which are smaller than a transistor size and a circuit distance of the high voltage element. (Koyama, [0227], “As an example, FIGS. 24A to 24C each show characteristics of a transistor in which an oxide semiconductor film including In, Sn, and Zn as main components and having a channel length L of 3 .mu.m and a channel width W of 10 .mu.m, and a gate insulating layer with a thickness of 100 nm are used. Note that V.sub.d was set to 10 V. In FIGS. 24A to 24C, the horizontal axis represents the gate voltage V.sub.g, the first vertical axis represents the drain current I.sub.d, and the second vertical axis represents the field-effect mobility .mu..sub.FE.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide different sizing of different transistor due to power requirements as this was a known technique in view of Koyama and would have been utilized for the art recognized purpose of sufficient electric characteristics can be ensured in a temperature range needed for operation of a transistor. With such characteristics, an integrated circuit having a novel function can be realized without decreasing the operation speed even when a transistor including an oxide semiconductor is also provided in an integrated circuit formed using a Si semiconductor. (Koyama, [0259])
Consider Claim 3:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 1, wherein the display panel is implemented as a chip different from the first chip. (Lee, [0108-0114], [0109], “The output buffer IC's 178A and 178B may be commonly connected in pairs of two to each of the TCP's 174 mounted with the DAC IC 176 in a liquid crystal display panel 180 by the CGO system. Each of the TCP's 174 may be electrically connected to the output buffer IC's 178A and 178B via pads provided at an upper portion of the liquid crystal display panel 180, and may be electrically connected to output pads provided at a data PCB 172. The data PCB 172 may transmit various control signals applied from the timing controller 110 and pixel data signals to the DAC IC's 176.”)
Consider Claim 4:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 1, wherein the decoder and the holding latch are integrated together with the buffer in the display panel. (Lee, [0108-0114], [0109], “The output buffer IC's 178A and 178B may be commonly connected in pairs of two to each of the TCP's 174 mounted with the DAC IC 176 in a liquid crystal display panel 180 by the CGO system. Each of the TCP's 174 may be electrically connected to the output buffer IC's 178A and 178B via pads provided at an upper portion of the liquid crystal display panel 180, and may be electrically connected to output pads provided at a data PCB 172. The data PCB 172 may transmit various control signals applied from the timing controller 110 and pixel data signals to the DAC IC's 176.”)
Consider Claim 6:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 5, wherein the data driver further includes a first multiplexer and a first demultiplexer, which are connected between the sampling latch and the first level shifter, and wherein the first multiplexer is integrated in the first chip, and wherein the first demultiplexer is integrated in the display panel. (Lee, [0073], “The demultiplexor 80 may allow pixel voltage signals input, which is received in the "k-by-k" order from the multiplexor 76, to be selectively applied to an n-number of output buffer cells of the 2n-number of output buffer cells included in the output buffer part 82 in the "k-by-k" order in response to a source input enable signal SIE received from the timing controller 58. Accordingly, the source input enable signal SIE may also have a bit number that corresponds to the frequency "j" in which the n-number of pixel voltage signals are divided similar to the selection control signal SEL.”)
Consider Claim 7:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 1, wherein the holding latch and the decoder are integrated in the first chip. (Choi, [0051-0055], Lee, [0070], “The DAC 70 may simultaneously convert the n-number of pixel data VD received from the latch part 68 into positive and negative pixel signals, and selectively output the positive and negative pixel voltage signals in response to a polarity control signal POL. Accordingly, the DAC 70 may include a positive (P) decoding part 72 and a negative (N) decoding part 74 that are commonly connected to the latch part 68, and a multiplexor (MUX) 76 for selecting output signals of the P decoding part 72 and the N decoding part 74.”)
Consider Claim 9:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 1, further comprising a timing controller configured to provide image data to the data driver, wherein the timing controller is integrated in a second chip different from the first chip. (Choi, [0046], “FIG. 3 illustrates a block circuit diagram of an organic light emitting display according to an exemplary embodiment of the present invention. Referring to FIG. 3, the organic light emitting display may include a pixel unit 230 including pixels 240 formed on a region where scan lines S1 to Sn are intersected with data lines D1 to Dm, a scan driver 210 for driving scan lines S1 to Sn, a data driver 220 for driving data lines D1 to Dm, and a timing controller 250 for controlling the scan driver 210 and the data driver 220. The data driver 220 may include at least one data driving circuit 222.”)
Consider Claim 10:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 1, further comprising a timing controller configured to provide image data to the data driver, wherein the timing controller is integrated in the first chip. (Lee, [0079], “The signal controller 92 may control various control signals such CLK, SSP, SSC, SOE, REV, POL, SEL1, and SEL2, for example, received from the timing controller 58 and the pixel data VD in order to output the various control signals to corresponding elements. The gamma voltage part 94 may sub-divide a plurality of gamma reference voltages input from a gamma reference voltage generator (not shown) for each gray level, and then output the sub-divided gamma reference voltages.”)
Consider Claim 11:
Choi discloses a display device comprising: (Choi, See Abstract.)
a display panel including a pixel connected to a data line, the display panel being configured to display an image; and (Choi, [0050], “The pixel unit 230 may receive a first power source ELVDD and a second power source ELVSS from an external source. The first power source ELVDD and the second power source ELVSS may be supplied to the pixel unit 230, and may be respectively supplied to the pixels 240. The pixels 240 receiving the first power source ELVDD and the second power source ELVSS may display images corresponding to data signals supplied from the data driving circuit 222.”)
a data driver configured to provide a data signal to the data line, wherein the data driver includes: (Choi, [0048] The data driver 220 may generate data signals in response to data driving control signals DCS from the timing controller 250. The data driver 220 may supply the generated data signals to the data lines D1 to Dm in sequence. The data driving circuit 222 may convert data supplied from an external source into data signals and supply the data signals to the data lines D1 to Dm. The data driving circuit 222 will be described in more detail below.”)
a shift register configured to generate a sampling signal; (Choi, [0053], “The shift register unit 223 may receive a source shift clock SSC and a source start pulse SSP from the timing controller 250. The shift register unit 223 receiving the source shift clock SSC and the source start pulse SSP may generate "i" sampling signals in sequence, while allowing the source start pulse SSP to be shifted depending on the source shift clock SSC. The shift register unit 223 may include "i" shift registers 2231 to 223i.”)
a sampling latch configured to latch image data in response to the sampling signal; (Choi, [0054], “The sampling latch unit 224 may store data in sequence depending on the sampling signals supplied in sequence from the shift register unit 223. The sampling latch unit 224 may include "i" sampling latches 2241 to 224i for storing "i" data. Each size of the sampling latches 2241 to 224i may be set to store k bit data. For the sake of discussion, this exemplary sampling latch unit 224 will be described assuming that k bit is 6 bits.”)
a holding latch configured to store an output of the sampling latch; (Choi, [0055], “The holding latch unit 225 may receive and store the data from the sampling latch unit 224 in response to a source output enable SOE signal. The holding latch unit 225 may supply the stored data to a level shifter 226. The holding latch unit 225 may include "i" holding latches 2251 to 225i. Each of the holding latches 2251 to 225i may be configured to store k bit data.”)
a decoder configured to convert an output of the holding latch into an analog signal; and (Choi, [0058], [0061], “FIG. 5 illustrates a block circuit diagram of an exemplary data signal generator as illustrated in FIGS. 4A and 4B. Referring to FIG. 5, the data signal generator 227 may include, for each channel, a first DAC 300, a second DAC 302 and a decoder unit 304.”)
a buffer configured to provide an output of the buffer to the data line. (Choi, [0060], “Referring to FIG. 4B, a buffer unit 228 may be connected between the data signal generator 227 and the data lines Dl to Di. The buffer unit 228 may supply the data signals supplied from the data signal generator 227 to the data lines D1 to Di.”)
wherein the sampling latch is implemented with a low voltage element, and wherein the level shifter and the holding latch are implemented with a high voltage element having a node level lower than a node level of the low voltage element. (Choi, [0062], “The first DAC 300 may receive the plurality of reference voltages (ref) from a gamma unit 229. The first DAC 300 may select a first reference voltage (ref1) and a second reference voltage (ref2) from the plurality of reference voltages (refs) depending on, e.g., a value of upper bits of the data. The first DAC 300 may receive the data from the level shifter 226, or directly from the holding latch unit 225, depending on the implementation.”)
Choi however does not specify wherein the data driver further includes a level shifter electrically connected between the sampling latch and the holding latch.
Lee however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide wherein the data driver further includes a level shifter electrically connected between the sampling latch and the holding latch. (Lee, [0108-0114], [0109], “The output buffer IC's 178A and 178B may be commonly connected in pairs of two to each of the TCP's 174 mounted with the DAC IC 176 in a liquid crystal display panel 180 by the CGO system. Each of the TCP's 174 may be electrically connected to the output buffer IC's 178A and 178B via pads provided at an upper portion of the liquid crystal display panel 180, and may be electrically connected to output pads provided at a data PCB 172. The data PCB 172 may transmit various control signals applied from the timing controller 110 and pixel data signals to the DAC IC's 176.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide portions of the data driver directly mounted on the display panel substrate as this was a known technique to those of skill in the art in view of Lee and would have been utilized for the purpose of reducing the number of components, preventing an increase in driving frequencies and reducing manufacturing costs. (Lee, [0110])
Nakajima however teaches that it was a technique known to those having ordinary skill in the art before the effective filing date of the invention to provide wherein the data driver further includes a level shifter electrically connected between the sampling latch and the holding latch, the level shifter being configured to convert a low voltage output from the sampling latch into a high voltage and to provide the high voltage to the holding latch. (Nakajima, [0081-0084], [0107], “Specifically, in the first and second horizontal driving systems 62, 63, level shift circuits 625, 635 and latch circuits 626, 636 for the H start pulse are provided and level shift circuit groups 627, 637 for the H clock pulse are provided corresponding to the respective shift stages. Moreover, level shift circuit groups 628, 638 for the display data are provided corresponding to the respective latch stages of the sampling and first latch circuits 622, 632. In the vertical driving system 64, only a level shift circuit 642 for the V start pulse and the V clock pulse is provided.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide level shifter connected between the sampling latch and the holding latch as this was a known technique in view of Nakajima and would have been utilized for the purpose of driving schemes that allow reduction in power consumption can be realized. (Nakajima, [0126])
Koyama however teaches that it was known technique wherein the low voltage element has a transistor size and a circuit distance, (Koyama, [0221], “FIGS. 21A to 21C show the gate voltage V.sub.g dependence of the drain current I.sub.d (a solid line) and the mobility .mu. (a dotted line) of the transistor having the structure illustrated in FIG. 23B where the offset length L.sub.off is 5 nm. The drain current I.sub.d is obtained by calculation under the assumption that the drain voltage is +1 V and the mobility .mu. is obtained by calculation under the assumption that the drain voltage is +0.1 V. FIG. 21A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating layer is 15 nm, FIG. 21B shows that of the transistor in the case where the thickness of the gate insulating layer is 10 nm, and FIG. 21C shows that of the transistor in the case where the thickness of the gate insulating layer is 5 nm.”)
which are smaller than a transistor size and a circuit distance of the high voltage element. (Koyama, [0227], “As an example, FIGS. 24A to 24C each show characteristics of a transistor in which an oxide semiconductor film including In, Sn, and Zn as main components and having a channel length L of 3 .mu.m and a channel width W of 10 .mu.m, and a gate insulating layer with a thickness of 100 nm are used. Note that V.sub.d was set to 10 V. In FIGS. 24A to 24C, the horizontal axis represents the gate voltage V.sub.g, the first vertical axis represents the drain current I.sub.d, and the second vertical axis represents the field-effect mobility .mu..sub.FE.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide different sizing of different transistor due to power requirements as this was a known technique in view of Koyama and would have been utilized for the art recognized purpose of sufficient electric characteristics can be ensured in a temperature range needed for operation of a transistor. With such characteristics, an integrated circuit having a novel function can be realized without decreasing the operation speed even when a transistor including an oxide semiconductor is also provided in an integrated circuit formed using a Si semiconductor. (Koyama, [0259])
Consider Claim 13:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 11, wherein the data driver further includes a first multiplexer and a first demultiplexer, which are connected between the sampling latch and the level shifter. (Lee, [0073], “The demultiplexor 80 may allow pixel voltage signals input, which is received in the "k-by-k" order from the multiplexor 76, to be selectively applied to an n-number of output buffer cells of the 2n-number of output buffer cells included in the output buffer part 82 in the "k-by-k" order in response to a source input enable signal SIE received from the timing controller 58. Accordingly, the source input enable signal SIE may also have a bit number that corresponds to the frequency "j" in which the n-number of pixel voltage signals are divided similar to the selection control signal SEL.”)
Consider Claim 14:
Choi discloses a electronic device comprising: (Choi, See Abstract.)
a processor configured to output input image data; and (Choi, [0049], “The timing controller 250 may generate a data driving control signal DCS and a scan driving control signal SCS depending on synchronization signals supplied from an external source. The data driving control signal DCS and the scan driving control signal SCS generated from the timing controller 250 may be supplied to the data driver 220 and to the scan driver 210, respectively,. The timing controller 250 may rearrange the data supplied from the external source and supply the rearranged data DATA to the data driver 220.”)
a display device configured to display an image, based on the input image data, wherein the display device includes: (Choi, [0050], “The pixel unit 230 may receive a first power source ELVDD and a second power source ELVSS from an external source. The first power source ELVDD and the second power source ELVSS may be supplied to the pixel unit 230, and may be respectively supplied to the pixels 240. The pixels 240 receiving the first power source ELVDD and the second power source ELVSS may display images corresponding to data signals supplied from the data driving circuit 222.”)
a display panel including a pixel connected to a data line; (Choi, [0048] The data driver 220 may generate data signals in response to data driving control signals DCS from the timing controller 250. The data driver 220 may supply the generated data signals to the data lines D1 to Dm in sequence. The data driving circuit 222 may convert data supplied from an external source into data signals and supply the data signals to the data lines D1 to Dm. The data driving circuit 222 will be described in more detail below.”)
a timing controller configured to convert the input image data into image data corresponding to an arrangement of the pixel in the display panel; and (Choi, [0049], “The timing controller 250 may generate a data driving control signal DCS and a scan driving control signal SCS depending on synchronization signals supplied from an external source. The data driving control signal DCS and the scan driving control signal SCS generated from the timing controller 250 may be supplied to the data driver 220 and to the scan driver 210, respectively,. The timing controller 250 may rearrange the data supplied from the external source and supply the rearranged data DATA to the data driver 220.”)
a data driver configured to generate a data signal, based on the image data, and provide the data signal to the data line, wherein the data driver includes: (Choi, [0048] The data driver 220 may generate data signals in response to data driving control signals DCS from the timing controller 250. The data driver 220 may supply the generated data signals to the data lines D1 to Dm in sequence. The data driving circuit 222 may convert data supplied from an external source into data signals and supply the data signals to the data lines D1 to Dm. The data driving circuit 222 will be described in more detail below.”)
a shift register configured to generate a sampling signal; (Choi, [0053], “The shift register unit 223 may receive a source shift clock SSC and a source start pulse SSP from the timing controller 250. The shift register unit 223 receiving the source shift clock SSC and the source start pulse SSP may generate "i" sampling signals in sequence, while allowing the source start pulse SSP to be shifted depending on the source shift clock SSC. The shift register unit 223 may include "i" shift registers 2231 to 223i.”)
a sampling latch configured to latch image data in response to the sampling signal; (Choi, [0054], “The sampling latch unit 224 may store data in sequence depending on the sampling signals supplied in sequence from the shift register unit 223. The sampling latch unit 224 may include "i" sampling latches 2241 to 224i for storing "i" data. Each size of the sampling latches 2241 to 224i may be set to store k bit data. For the sake of discussion, this exemplary sampling latch unit 224 will be described assuming that k bit is 6 bits.”)
a holding latch configured to store an output of the sampling latch; (Choi, [0055], “The holding latch unit 225 may receive and store the data from the sampling latch unit 224 in response to a source output enable SOE signal. The holding latch unit 225 may supply the stored data to a level shifter 226. The holding latch unit 225 may include "i" holding latches 2251 to 225i. Each of the holding latches 2251 to 225i may be configured to store k bit data.”)
a decoder configured to convert an output of the holding latch into an analog signal; and (Choi, [0058], [0061], “FIG. 5 illustrates a block circuit diagram of an exemplary data signal generator as illustrated in FIGS. 4A and 4B. Referring to FIG. 5, the data signal generator 227 may include, for each channel, a first DAC 300, a second DAC 302 and a decoder unit 304.”)
a buffer configured to provide an output of the decoder to the data line. (Choi, [0060], “Referring to FIG. 4B, a buffer unit 228 may be connected between the data signal generator 227 and the data lines Dl to Di. The buffer unit 228 may supply the data signals supplied from the data signal generator 227 to the data lines D1 to Di.”)
wherein the first chip includes a low voltage element having a node level higher than a node level of a high voltage element integrated in the display panel, and does not include the high voltage element. (Choi, [0062], “The first DAC 300 may receive the plurality of reference voltages (ref) from a gamma unit 229. The first DAC 300 may select a first reference voltage (ref1) and a second reference voltage (ref2) from the plurality of reference voltages (refs) depending on, e.g., a value of upper bits of the data. The first DAC 300 may receive the data from the level shifter 226, or directly from the holding latch unit 225, depending on the implementation.”)
Choi however does not specify wherein the sampling latch is integrated in a first chip different from the display panel, and wherein the buffer is integrated in the display panel.
Lee however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide wherein the sampling latch is integrated in a first chip different from the display panel, and wherein the buffer is integrated in the display panel. (Lee, [0108-0114], [0109], “The output buffer IC's 178A and 178B may be commonly connected in pairs of two to each of the TCP's 174 mounted with the DAC IC 176 in a liquid crystal display panel 180 by the CGO system. Each of the TCP's 174 may be electrically connected to the output buffer IC's 178A and 178B via pads provided at an upper portion of the liquid crystal display panel 180, and may be electrically connected to output pads provided at a data PCB 172. The data PCB 172 may transmit various control signals applied from the timing controller 110 and pixel data signals to the DAC IC's 176.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide portions of the data driver directly mounted on the display panel substrate as this was a known technique to those of skill in the art in view of Lee and would have been utilized for the purpose of reducing the number of components, preventing an increase in driving frequencies and reducing manufacturing costs. (Lee, [0110])
Choi in view of Lee however do not specify the arrangement of a first level shifter connected between the sampling latch and the holding latch and configured to covert a low voltage output from the sampling latch into a high voltage and to provide the high voltage to the holding latch.
Nakajima however teaches that it was a technique known to those having ordinary skill in the art before the effective filing date of the invention to provide a first level shifter connected between the sampling latch and the holding latch and configured to covert a low voltage output from the sampling latch into a high voltage and to provide the high voltage to the holding latch. (Nakajima, [0107], “Specifically, in the first and second horizontal driving systems 62, 63, level shift circuits 625, 635 and latch circuits 626, 636 for the H start pulse are provided and level shift circuit groups 627, 637 for the H clock pulse are provided corresponding to the respective shift stages. Moreover, level shift circuit groups 628, 638 for the display data are provided corresponding to the respective latch stages of the sampling and first latch circuits 622, 632. In the vertical driving system 64, only a level shift circuit 642 for the V start pulse and the V clock pulse is provided.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide level shifter connected between the sampling latch and the holding latch as this was a known technique in view of Nakajima and would have been utilized for the purpose of driving schemes that allow reduction in power consumption can be realized. (Nakajima, [0126])
Koyama however teaches that it was known technique wherein the low voltage element has a transistor size and a circuit distance, (Koyama, [0221], “FIGS. 21A to 21C show the gate voltage V.sub.g dependence of the drain current I.sub.d (a solid line) and the mobility .mu. (a dotted line) of the transistor having the structure illustrated in FIG. 23B where the offset length L.sub.off is 5 nm. The drain current I.sub.d is obtained by calculation under the assumption that the drain voltage is +1 V and the mobility .mu. is obtained by calculation under the assumption that the drain voltage is +0.1 V. FIG. 21A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating layer is 15 nm, FIG. 21B shows that of the transistor in the case where the thickness of the gate insulating layer is 10 nm, and FIG. 21C shows that of the transistor in the case where the thickness of the gate insulating layer is 5 nm.”)
which are smaller than a transistor size and a circuit distance of the high voltage element. (Koyama, [0227], “As an example, FIGS. 24A to 24C each show characteristics of a transistor in which an oxide semiconductor film including In, Sn, and Zn as main components and having a channel length L of 3 .mu.m and a channel width W of 10 .mu.m, and a gate insulating layer with a thickness of 100 nm are used. Note that V.sub.d was set to 10 V. In FIGS. 24A to 24C, the horizontal axis represents the gate voltage V.sub.g, the first vertical axis represents the drain current I.sub.d, and the second vertical axis represents the field-effect mobility .mu..sub.FE.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide different sizing of different transistor due to power requirements as this was a known technique in view of Koyama and would have been utilized for the art recognized purpose of sufficient electric characteristics can be ensured in a temperature range needed for operation of a transistor. With such characteristics, an integrated circuit having a novel function can be realized without decreasing the operation speed even when a transistor including an oxide semiconductor is also provided in an integrated circuit formed using a Si semiconductor. (Koyama, [0259])
Consider Claim 16:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the electronic device of claim 14, wherein the decoder and the holding latch are integrated together with the buffer in the display panel. (Lee, [0108-0114], [0109], “The output buffer IC's 178A and 178B may be commonly connected in pairs of two to each of the TCP's 174 mounted with the DAC IC 176 in a liquid crystal display panel 180 by the CGO system. Each of the TCP's 174 may be electrically connected to the output buffer IC's 178A and 178B via pads provided at an upper portion of the liquid crystal display panel 180, and may be electrically connected to output pads provided at a data PCB 172. The data PCB 172 may transmit various control signals applied from the timing controller 110 and pixel data signals to the DAC IC's 176.”) The Office notes that it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950).
Consider Claim 18:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the electronic device of claim 17, wherein the data driver further includes a first multiplexer and a first demultiplexer, which are connected between the sampling latch and the first level shifter, and wherein the first multiplexer is integrated in the first chip, and wherein the first demultiplexer is integrated in the display panel. (Lee, [0073], “The demultiplexor 80 may allow pixel voltage signals input, which is received in the "k-by-k" order from the multiplexor 76, to be selectively applied to an n-number of output buffer cells of the 2n-number of output buffer cells included in the output buffer part 82 in the "k-by-k" order in response to a source input enable signal SIE received from the timing controller 58. Accordingly, the source input enable signal SIE may also have a bit number that corresponds to the frequency "j" in which the n-number of pixel voltage signals are divided similar to the selection control signal SEL.”)
Consider Claim 20:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the electronic device of claim 14, wherein the electronic device is one of a smart watch, a mobile phone, a smartphone, a portable computer, a tablet personal computer (PC), a watch phone, an automotive display, a smart glass, a portable multimedia player (PMP), a navigation system, or an ultra mobile computer (UMPC), a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device. (Choi, [0004], “Various flat panel display devices having reduced weight and volume compared to comparable cathode ray tubes (CRTs) have been developed. These flat panel display devices include e.g., a liquid crystal display, a field emission display, a plasma display panel, an organic light emitting display, etc. These exemplary displays may operate differently to display an image.”)
Claim Rejections - 35 USC § 103
Claim(s) 5, 8, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi U.S. Patent Application Publication No. 2007/0139313 A1 in view of Lee et al. U.S. Patent Application Publication No. 2003/00858565 A1 in view of Nakajima et al. U.S. Patent Application Publication No. 2002/0135556 A1 in view of Koyama U.S. Patent Application Publication No. 2012/0062529 A1 as applied to claim 7 above, and further in view of Haga et al. U.S. Patent Application Publication No. 2003/0067434 A1 hereinafter Haga.
Consider Claim 5:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 4, wherein the level shifter is integrated in the display panel. (Choi, [0056], “The level shifter 226 may raise a voltage level of the data supplied from the holding latch unit 225. The level shifter 226 may supply the data with a raised voltage level to the data signal generator 227. In this regard, the data driver 220 may receive data having a low voltage level and may raise the voltage level of the data to a high voltage level by employing the level shifter 226.”)
Choi in view of Lee however does not specify wherein the level shifter is integrated in the display panel.
Haga wherein the level shifter is integrated in the display panel. (Haga, [0292-0303], [0294], “The display device substrate 101 has, built in, the level shifter/timing buffer 108, scanning circuit 109, S/P converter 1801, level shifter 104, latch circuit 105, DAC 106, voltage-current converting circuit/current output buffer 801 and display area 110 and is connected to the controller IC 102. The level shifter 104, serial/parallel-converting circuit 1801, latch circuit 105, DAC 106 and voltage-current converting circuit/current output buffer 801 are disposed in the order mentioned, and the voltage-current converting circuit/current output buffer 801 is connected to the column-side of the display area 10.” See Fig. 30.)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide integration of the level shifter in the panel as this was a known technique in view of Haga and would have been utilized for the purpose of power consumption is reduced greatly. (Haga, [0301]) The Office notes that it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The Office notes that it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950).
Consider Claim 8:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the display device of claim 7, however do not specify wherein the data driver further includes a second level shifter connected between the decoder and the buffer, and wherein the second level shifter is integrated in the display panel.
Haga however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention wherein the data driver further includes a level shifter connected between the decoder and the buffer, and wherein the level shifter is integrated in the display panel. (Haga, [0292-0303], [0294], “The display device substrate 101 has, built in, the level shifter/timing buffer 108, scanning circuit 109, S/P converter 1801, level shifter 104, latch circuit 105, DAC 106, voltage-current converting circuit/current output buffer 801 and display area 110 and is connected to the controller IC 102. The level shifter 104, serial/parallel-converting circuit 1801, latch circuit 105, DAC 106 and voltage-current converting circuit/current output buffer 801 are disposed in the order mentioned, and the voltage-current converting circuit/current output buffer 801 is connected to the column-side of the display area 10.” See Fig. 30.)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide integration of the level shifter in the panel as this was a known technique in view of Haga and would have been utilized for the purpose of power consumption is reduced greatly. (Haga, [0301]) The Office notes that it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950).
Consider Claim 19:
Choi in view of Lee in view of Nakajima in view of Koyama disclose the electronic device of claim 14, wherein the holding latch and the decoder are integrated in the first chip, wherein the data driver further includes a level shifter connected between the decoder and the buffer, and wherein the level shifter is integrated in the display panel.
Choi in view of Lee in view of Nakajima however does not specify wherein the level shifter is integrated in the display panel.
Haga however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention wherein the holding latch and the decoder are integrated in the first chip, wherein the data driver further includes a level shifter connected between the decoder and the buffer, and wherein the level shifter is integrated in the display panel. (Haga, [0292-0303], [0294], “The display device substrate 101 has, built in, the level shifter/timing buffer 108, scanning circuit 109, S/P converter 1801, level shifter 104, latch circuit 105, DAC 106, voltage-current converting circuit/current output buffer 801 and display area 110 and is connected to the controller IC 102. The level shifter 104, serial/parallel-converting circuit 1801, latch circuit 105, DAC 106 and voltage-current converting circuit/current output buffer 801 are disposed in the order mentioned, and the voltage-current converting circuit/current output buffer 801 is connected to the column-side of the display area 10.” See Fig. 30.)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide integration of the level shifter in the panel as this was a known technique in view of Haga and would have been utilized for the purpose of power consumption is reduced greatly. (Haga, [0301]) The Office notes that it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179. The Office notes that it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950).
Claim Rejections - 35 USC § 103
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi U.S. Patent Application Publication No. 2007/0139313 A1 in view of Lee et al. U.S. Patent Application Publication No. 2003/00858565 A1 in view of Koyama U.S. Patent Application Publication No. 2012/0062529 A1 in view of Nakajima et al. U.S. Patent Application Publication No. 2002/0135556 A1 as applied to claim 16 above, and further in view of Haga et al. U.S. Patent Application Publication No. 2003/0067434 A1 in view of Ahn et al. U.S. Patent Application Publication No. 2021/0134205 A1 hereinafter Ahn.
Consider Claim 17:
Choi in view of Lee in view of Koyama in view of Nakajima disclose the electronic device of claim 16, that includes a level shifter, sampling latch, and holding latch however does not specify wherein the data driver further includes a first level shifter connected between the sampling latch and the holding latch, and wherein the first level shifter is integrated in the display panel.
Haga however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention wherein the data driver further includes a first level shifter connected between the sampling latch and the holding latch, and wherein the first level shifter is integrated in the display panel. (Haga, [0292-0303], [0294], “The display device substrate 101 has, built in, the level shifter/timing buffer 108, scanning circuit 109, S/P converter 1801, level shifter 104, latch circuit 105, DAC 106, voltage-current converting circuit/current output buffer 801 and display area 110 and is connected to the controller IC 102. The level shifter 104, serial/parallel-converting circuit 1801, latch circuit 105, DAC 106 and voltage-current converting circuit/current output buffer 801 are disposed in the order mentioned, and the voltage-current converting circuit/current output buffer 801 is connected to the column-side of the display area 10.” See Fig. 30.)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide integration of the level shifter in the panel as this was a known technique in view of Haga and would have been utilized for the purpose of power consumption is reduced greatly. (Haga, [0301]) The Office notes that it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179.
Kim teaches that it was a known technique to those of skill in the art to provide wherein the data driver further includes a level shifter connected between the sampling latch and the holding latch. (Kim, [0040], “Referring to FIG. 1, the data driver 100 includes a shift register 110, a first latch unit 120, a selector 130, a level shifter unit 140, a second latch unit 150, a digital-to-analog converter 160, and an output unit 170.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide the claimed arrangement in view of Kim as this would have been utilized for the purpose of the size of the data driver may be reduced without a reduction in performance, and thus chip manufacturing costs may also be reduced. (Kim, [0066]) The Office notes that it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950).
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached on 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michael J Jansen II/ Primary Examiner, Art Unit 2626
