Prosecution Insights
Last updated: July 17, 2026
Application No. 19/096,977

DISPLAY DEVICE FOR EXAMINING THE STATUS OF A SOURCE LINE AND INTEGRATED CIRCUIT THEREOF

Non-Final OA §103
Filed
Apr 01, 2025
Priority
Apr 02, 2024 — provisional 63/572,998
Examiner
AU, SCOTT D
Art Unit
2624
Tech Center
2600 — Communications
Assignee
Novatek Microelectronics Corp.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 7m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
402 granted / 523 resolved
+14.9% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
20 currently pending
Career history
545
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
91.7%
+51.7% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 523 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Huang Bing Kai (TWI607673B hereinafter Huang) in view of Cho et al. (US 2019/0189058 hereinafter Cho), and Chen, Chang-Hung (TW M627999 hereinafter Chen). Referring to claim 1, Huang discloses an integrated circuit applicable to inspecting a display panel (see Huang- attachment highlighted section; Referring to FIG. 1 and FIG. 2, a first embodiment of the failure detection system of the present invention includes an illumination array 1, a failure detection device 2, and a display 29.), comprising: a plurality of analog front-end (AFE) circuits (Fig. 7; 274), each AFE circuit comprises a non-inverting input terminal coupled to a first predetermined voltage (Fig. 7; non-inverting terminal (+) is coupled to voltage Vdif) and an inverting input terminal (Fig. 7; inverting terminal (-)); and a plurality of multiplexer groups (Fig. 4; multiplexers 25a-25b), and each multiplexer is correspondingly configured in relation to one source line of the display panel (see Huang- attachment highlighted section; The second multiplexer 25b receives the second selection signal S1b, and electrically connects the plurality of data lines to receive the voltages Vd1 V Vd4 on the plurality of data lines, and selects the plurality according to the second selection signal S1b. One of the voltages on the data line, Vd2, is the output voltage of the output of the light-emitting diode unit 11f to be detected.) and each multiplexer (Fig. 4; multiplexers 25a-25b) comprises a first terminal coupled to the source line of the display panel and a plurality of second terminals given by different settings, and the source line is configured correspondingly to one of the different settings by electrically connecting the first terminal and a selected second terminal from the plurality of second terminals (see Huang- attachment highlighted section; The second multiplexer 25b receives the second selection signal S1b, and electrically connects the plurality of data lines to receive the voltages Vd1 V Vd4 on the plurality of data lines, and selects the plurality according to the second selection signal S1b. One of the voltages on the data line, Vd2, is the output voltage of the output of the light-emitting diode unit 11f to be detected.). However, Huang does not explicitly disclose wherein each multiplexer group comprises a plurality of multiplexers and wherein one of the plurality of second terminals is alternatively coupled to the inverting input terminal of one of the plurality of AFE circuits corresponding to one of the plurality of multiplexer groups. In an analogous art, Cho discloses wherein each multiplexer group comprises a plurality of multiplexers (Cho- [0071-0072], Fig. 6; switchable output units 312 and 314, each comprises a plurality of MUXs). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Cho to the system of Huang in order to reduce the manufacturing cost of the chip on film COF. However, Huang in view of Cho does not explicitly disclose wherein one of the plurality of second terminals is alternatively coupled to the inverting input terminal of one of the plurality of AFE circuits corresponding to one of the plurality of multiplexer groups. In an analogous art, Chen discloses wherein one of the plurality of second terminals is alternatively coupled to the inverting input terminal of one of the plurality of AFE circuits corresponding to one of the plurality of multiplexer groups (Chen- Fig. 16-17; each MUX is connected to the inverting terminal of each circuit AFE). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Chen to the system of Huang in view of Cho in order to improve the touch control performance. Claim Objections Claims 2-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Referring to claim 2, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein when one end of an inspected source line of the display panel near the integrated circuit coupled to a first multiplexer of a first multiplexer group among the plurality of multiplexer groups is connected to the inverting input terminal of a first AFE circuit corresponding to the first multiplexer group and provided with the first predetermined voltage and the other end of the inspected source line far from the integrated circuit is configured to be floating, and non-inspected source lines which are connected to multiplexers other than the first multiplexer are provided with another voltage different from the first predetermined voltage through the multiplexers other than the first multiplexer, whether the inspected source line is short-circuited to a non-inspected source line is examined by the first AFE circuit”. Referring to claims 3-5 are objected upon dependent on the claim 2. Referring to claim 6, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein when one end of an inspected source line of the display panel near the integrated circuit coupled to a first multiplexer of a first multiplexer group among the plurality of multiplexer groups is connected to the inverting input terminal of a first AFE circuit corresponding to the first multiplexer group and provided with the first predetermined voltage and the other end of the inspected source line far from the integrated circuit is configured to be floating, and gate lines of the display panel are provided with another voltage different from the first predetermined voltage, whether the inspected source line is short- circuited to one of the gate lines is examined by the first AFE circuit”. Referring to claims 7-11 are objected upon dependent on the claim 6. Referring to claim 12, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein when one end of an inspected source line of the display panel near the integrated circuit coupled to a first multiplexer of a first multiplexer group among the plurality of multiplexer groups is connected to the inverting input terminal of the first AFE circuit corresponding to the first multiplexer group and provided with the first predetermined voltage and the other end of the inspected source line far from the integrated circuit is provided with a second predetermined voltage, and non-inspected source lines which are connected to multiplexers other than the first multiplexer are electrically connected to the plurality of second terminals which are kept in a high impendence state, whether the inspected source line is open-circuit is examined by the first AFE circuit”. Referring to claims 13-18 are objected upon dependent on the claim 12. Allowable Subject Matter Claims 19-35 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Claims 19-35 are allowed since certain key features of the claimed invention are not taught or fairly suggested by prior art. Referring to claim 19, the prior art of record, does not teach, disclose or suggest the claimed limitations of (in combination with all other limitations in the claim), “A display device comprising: an integrated circuit, comprising a plurality of analog front-end (AFE) circuits and a plurality of multiplexer groups; and a display panel, comprising: source lines, each source line comprising one end near the integrated circuit and the other end far from the integrated circuit, wherein an inspected source line among the plurality of source lines is controlled to be electrically connected or disconnected to a first AFE circuit among the plurality of AFE circuits by a first multiplexer of a first multiplexer group of the plurality of multiplexer groups; gate lines; a testing wire, being provided with a second predetermined voltage to the inspected source line; and a plurality of testing switches, wherein each testing switch is coupled between the testing wire and the other end of one of the plurality of source lines far from the integrated circuit and configured to perform at least one of the following actions: electrically connect the testing wire and the inspected source line when the first AFE circuit examines whether the inspected source line is open-circuit; and electrically disconnect the testing wire and the inspected source line when the first AFE circuit examines whether the inspected source line is short-circuited to another source line; and electrically disconnect the testing wire and the inspected source line when the first AFE circuit examines whether the inspected source line is short-circuited to a gate line.”. Referring to claims 20-35 are allowable based upon dependent on the independent claim 19. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT D AU whose telephone number is (571)272-5948. The examiner can normally be reached M-F. General 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SCOTT D AU/Examiner, Art Unit 2624
Read full office action

Prosecution Timeline

Apr 01, 2025
Application Filed
Apr 21, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
88%
With Interview (+11.0%)
2y 10m (~1y 7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 523 resolved cases by this examiner. Grant probability derived from career allowance rate.

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