DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 8-11, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Djahanshahi et al (Patent 9608647, further referred to as Djahanshahi).
As to claim 1, Djahanshahi teaches a method (fig 1, 5, 6, and 13), comprising:
performing a sweep of biasing voltage steps (fig 6, (214), column 15 lines 39-42) applied to an auxiliary varactor (16) of a voltage-controlled oscillator (VCO)(102) of a phase locked loop (PLL)(fig 13, VCO 102 is part of a PLL);
for each of a plurality of the biasing voltage steps corresponding to the sweep:
determining a frequency difference between a reference clock signal of the PLL and a VCO clock (column 15 lines 42-47); and
determining a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps (column 15 lines 49-52, the controller picks the lowest frequency difference, thus it must compare the frequency differences at step with one another in order to find which is the lowest); and
Selecting on a plurality of biasing voltage steps as a target biasing voltage for the auxiliary varactor based on the calculated differences (column 15 lines 49-52).
As to claim 2, Djahanshahi teaches generating the plurality of biasing voltage steps; converting the plurality of biasing voltage steps into corresponding analog signals; and supplying the corresponding analog signals to the auxiliary varactor (column 23 lines 41-57).
As to claim 3, Djahanshahi teaches wherein the plurality of biasing voltage steps is separated by a voltage increment that induces a corresponding step change to the VCO clock (column 10 lines 15-24,line 56-column 11 line 10, each of the RATE steps has a voltage increment step) .
As to claim 6, Djahanshahi teaches performing a calibration of the VCO via calibrating signals provided by a controller (104)(column 11 lines 20-44).
As to claim 8, Djahanshahi teaches wherein the performing of the sweep of biasing voltage steps is implemented at a predetermined time period (column 3 lines 9-32, performed at start up).
As to claim 9, Djahanshahi teaches wherein the VCO is a part of the PLL (702) that implements frequency and phase tracking (at PFD) of a reference signal (REFCLK).
As to claim 10, Djahanshahi teaches a system (fig 1, 5, 6, and 13), comprising:
A phase locked loop (fig 13, 702) including a voltage controlled oscillator (102);
A digital to analog converter (DAC)(within 104) coupled to an auxiliary varactor of the VCO (fig 1, (16)(column 23 lines 41-57),
A controller (104) coupled to the VCO and the DAC, the controller configured to:
perform a sweep of biasing voltage steps (fig 6, (214), column 15 lines 39-42) applied to an auxiliary varactor (16) of a voltage-controlled oscillator (VCO)(102) of a phase locked loop (PLL)(fig 13, VCO 102 is part of a PLL);
for each of a plurality of the biasing voltage steps corresponding to the sweep:
determine a frequency difference between a reference clock signal of the PLL and a VCO clock (column 15 lines 42-47); and
determine a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps (column 15 lines 49-52, the controller picks the lowest frequency difference, thus it must compare the frequency differences at step with one another in order to find which is the lowest); and
Select on a plurality of biasing voltage steps as a target biasing voltage for the auxiliary varactor based on the calculated differences (column 15 lines 49-52).
As to claim 11, Djahanshahi teaches generating the plurality of biasing voltage steps; converting the plurality of biasing voltage steps into corresponding analog signals; and supplying the corresponding analog signals to the auxiliary varactor (column 23 lines 41-57).
As to claim 13, Djahanshahi teaches wherein the plurality of biasing voltage steps is separated by a voltage increment that induces a corresponding step change to the VCO clock (column 10 lines 15-24, line 56-column 11 line 10, each of the RATE steps has a voltage increment step) .
As to claim 15, Djahanshahi teaches wherein the performing of the sweep of biasing voltage steps is implemented at a predetermined time period (column 3 lines 9-32, performed at start up).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Djahanshahi
As to claim 7, Djahanshahi teaches a method (fig 1, 5, 6, and 13), comprising:
performing a sweep of biasing voltage steps (fig 6, (214), column 15 lines 39-42) applied to an auxiliary varactor (16) of a voltage-controlled oscillator (VCO)(102) of a phase locked loop (PLL)(fig 13, VCO 102 is part of a PLL);
for each of a plurality of the biasing voltage steps corresponding to the sweep:
determining a frequency difference between a reference clock signal of the PLL and a VCO clock (column 15 lines 42-47); and
determining a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps (column 15 lines 49-52, the controller picks the lowest frequency difference, thus it must compare the frequency differences at step with one another in order to find which is the lowest); and
Selecting on a plurality of biasing voltage steps as a target biasing voltage for the auxiliary varactor based on the calculated differences (column 15 lines 49-52); and storing data and relationships related to parameters of the frequency signals (column 17 lines 5-14, lines 30-37, and column 19 lines 13-15).
Djahanshahi does not teach ranking the stored data.
As would have been recognized by obvious to a person of ordinary skill in the art to organize the data in a ranking system is done merely as a design choice to storing the data in a notorious well known in the art fashion for data access. As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to modify the data storing taught in Djahanshahi with a ranking system as doing so would be a mere matter of design choice to choosing a notoriously well known in the art storing system.
As to claim 14, Djahanshahi teaches determine a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps (column 15 lines 49-52, the controller picks the lowest frequency difference, thus it must compare the frequency differences at step with one another in order to find which is the lowest) and storing data and relationships related to parameters of the frequency signals (column 17 lines 5-14, lines 30-37, and column 19 lines 13-15). It would be obvious to a person of ordinary skill in the art to organize the data in a ranking system is done merely as a design choice to storing the data in a notorious well known in the art fashion for data access.
Claim(s) 16-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Djahanshahi in view of Plouchart et al (Pub 2023/0336123, further referred to as Plouchart).
As to claim 16, Djahanshahi teaches a system (fig 1, 5, 6, and 13), comprising:
A phase locked loop (fig 13, 702) including a voltage controlled oscillator (102);
A digital to analog converter (DAC)(within 104) coupled to an auxiliary varactor of the VCO (fig 1, (16)(column 23 lines 41-57),
A controller (104) coupled to the VCO and the DAC, the controller configured to:
perform a sweep of biasing voltage steps (fig 6, (214), column 15 lines 39-42) applied to an auxiliary varactor (16) of a voltage-controlled oscillator (VCO)(102) of a phase locked loop (PLL)(fig 13, VCO 102 is part of a PLL);
for each of a plurality of the biasing voltage steps corresponding to the sweep:
determine a frequency difference between a reference clock signal of the PLL and a VCO clock (column 15 lines 42-47); and
determine a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps (column 15 lines 49-52, the controller picks the lowest frequency difference, thus it must compare the frequency differences at step with one another in order to find which is the lowest); and
Select on a plurality of biasing voltage steps as a target biasing voltage for the auxiliary varactor based on the calculated differences (column 15 lines 49-52).
Djahanshahi does not teach another varactor.
Plouchart teaches forming a VCO circuit (fig 3, (324), fig 7, (700)) in a PLL (fig 11) where a calibration circuit (1110) controls a plurality of varactors (700-n) based on a tuning signal (paragraphs 93-95). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine PLL circuit taught in Djahanshahi with the varactor VCO in Plouchart in order to improve VCO tuning and range.
As to claim 17, Djahanshahi teaches an apparatus (fig 1, 5, 6, and 13), comprising:
A voltage controlled oscillator (102);
A digital to analog converter (DAC)(within 104) coupled to an auxiliary varactor of the VCO (fig 1, (16)(column 23 lines 41-57),
A controller (104) coupled to the VCO and the DAC, the controller configured to:
perform a sweep of biasing voltage steps (fig 6, (214), column 15 lines 39-42) applied to an auxiliary varactor (16) of a voltage-controlled oscillator (VCO)(102) of a phase locked loop (PLL)(fig 13, VCO 102 is part of a PLL);
for each of a plurality of the biasing voltage steps corresponding to the sweep:
determine a frequency difference between a reference clock signal of the PLL and a VCO clock (column 15 lines 42-47); and
determine a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps (column 15 lines 49-52, the controller picks the lowest frequency difference, thus it must compare the frequency differences at step with one another in order to find which is the lowest); and
Select on a plurality of biasing voltage steps as a target biasing voltage for the auxiliary varactor based on the calculated differences (column 15 lines 49-52).
Djahanshahi does not teach another varactor.
Plouchart teaches forming a VCO circuit (fig 3, (324), fig 7, (700)) in a PLL (fig 11) where a calibration circuit (1110) controls a plurality of varactors (700-n) based on a tuning signal (paragraphs 93-95). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine PLL circuit taught in Djahanshahi with the varactor VCO in Plouchart in order to improve VCO tuning and range.
As to claim 18, Djahanshahi teaches determine a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps (column 15 lines 49-52, the controller picks the lowest frequency difference, thus it must compare the frequency differences at step with one another in order to find which is the lowest) and storing data and relationships related to parameters of the frequency signals (column 17 lines 5-14, lines 30-37, and column 19 lines 13-15). It would be obvious to a person of ordinary skill in the art to organize the data in a ranking system is done merely as a design choice to storing the data in a notorious well known in the art fashion for data access.
As to claim 20, Djahanshahi teaches wherein the plurality of biasing voltage steps is separated by a voltage increment that induces a corresponding step change to the VCO clock (column 10 lines 15-24, line 56-column 11 line 10, each of the RATE steps has a voltage increment step).
Allowable Subject Matter
Claims 4, 5, 12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited prior art teach or suggest that predetermined gap is used to identify pairs of biasing and wherein the determined difference is based on a comparison between the VCO frequency differences associated with each of the identified pairs predetermined data pairs are used; as is recited in claims 4, 5, 12, and 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY M SHIN whose telephone number is (571)270-7356. The examiner can normally be reached M-F 9am-6pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEFFREY M SHIN/Primary Examiner, Art Unit 2849
Prosecution Insights