Prosecution Insights
Last updated: April 19, 2026
Application No. 19/096,997

DISPLAY PANEL INCLUDING TEST TRANSISTOR AND DEFECT DETECTION METHOD FOR DISPLAY PANEL

Non-Final OA §102§103
Filed
Apr 01, 2025
Examiner
HALEY, JOSEPH R
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
86%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
881 granted / 1114 resolved
+17.1% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
37 currently pending
Career history
1151
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
55.0%
+15.0% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1114 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 5 objected to because of the following informalities: “cathode terminal of an inorganic light-emitting element is connected to the cathode terminal” should read -- cathode terminal of an inorganic light-emitting element is connected to the cathode pad--. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2 and 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2020/0302840). In regard to claim 1, Kim et al. teach a display panel comprising: a plurality of pixel circuits configured to drive a plurality of inorganic light-emitting elements (fig. 1B and paragraph 106); a plurality of pixel electrodes configured to connect the plurality of inorganic light-emitting elements to the plurality of pixel circuits (fig. 14 CP1 and paragraph 236. Kim et al. shows the anode is connected to M6, M7 and M8 through CP1); a plurality of test transistors connected to the plurality of pixel circuits through the plurality of pixel electrodes (M8 connected to CP1 through BRP 4 and 5); and at least one processor (paragraph 80) configured to: apply a voltage to at least one of the plurality of pixel circuits; and detect whether at least one of the plurality of pixel electrodes is defective based on current flowing through one of the plurality of test transistors according to the voltage applied to the at least one of the plurality of pixel circuits (fig. 8 and fig. 14 CP1. If the pixel electrode CP1 is defective no current will flow through the test transistor and will register as defective). In regard to claims 2 and 10, Kim et al. teach a plurality of metal layers comprising: a first metal layer and a second metal layer on which the plurality of pixel circuits and the plurality of test transistors are formed (fig. 15 ACT1, ACT2 and GE); a third metal layer on which a driving electrode for supplying a driving voltage to the plurality of pixel circuits is formed (fig. 15 layer VIA2, PL1 and paragraph 114); and a fourth metal layer on which a ground electrode for supplying a ground voltage to the plurality of pixel circuits is formed, and wherein the plurality of pixel electrodes are formed on the fourth metal layer (fig. 15, PL2. The electrode CP1 is connected to AE via a metal layer on the layer including PL2. The via and the electrode CP1 are a single element). Claim 7 is the method corresponding to the apparatus of claim 1 and is rejected on the same grounds. In regard to claim 8, Kim et al. teach wherein each of the plurality of pixel electrodes comprise an anode pad to which a test transistor of the plurality of test transistors is connected (CP1), and wherein the detecting comprises, based on no current flowing through the test transistor according to the voltage, detecting that the anode pad is defective (figs. 8 and 14. If CP1 is broken no current will flow through the test transistor). In regard to claim 9, Kim et al. teach wherein, based on the anode pad being opened or a connection wiring between a pixel circuit of the plurality of pixel circuits and the anode pad through a via being disconnected, no current flows through the test transistor in a state in which the voltage is applied to the pixel circuit during a defect test (figs. 8 and 14. If CP1 is broken no current will flow through the test transistor). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Zhao (US 2024/0040865). In regard to claim 3, Kim et al. teach all the elements of claim 3 except wherein each of the plurality of pixel electrodes comprise: a cathode pad connected to the ground electrode; and an anode pad connected to a pixel circuit of the plurality of pixel circuits. Zhao teaches wherein each of the plurality of pixel electrodes comprise: a cathode pad connected to the ground electrode (fig. 3 element 284 is connected to element 33); and an anode pad connected to a pixel circuit of the plurality of pixel circuits (element 282 is connected to elements T1, T3 and 311). The two are analogous art because they both deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kim et al. with the connections of Zhao. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kim et al. with the connections of Zhao because the connections of Zhao would work equally as well in the apparatus of Kim et al. as they do separately. One of ordinary skill in the art would recognize the connections of Zhao would provide predictable results and would improve manufacturing efficiency. In regard to claims 4 and 11, Zhao teaches wherein the pixel circuit of the plurality of pixel circuits is connected to the anode pad through a first via (fig. 3, T1 is connected to element 282 and the anode through via K5); and wherein a test transistor of the plurality of test transistors is connected to the anode pad through a second via (elements K4 and T3). In regard to claim 5, Zhao teaches wherein the plurality of inorganic light-emitting elements are mounted on the display panel such that a cathode terminal of an inorganic light-emitting element is connected to the cathode terminal (fig. 3 element 33 is connected to element 284) and an anode terminal of the inorganic light-emitting element is connected to the anode pad (element 282 is connected to element 311). In regard to claims 6, Kim et al. teach wherein, based on the anode pad being opened or a connection wiring between the pixel circuit and the anode pad through the first via being disconnected, no current flows through the test transistor in a state in which the voltage is applied to the pixel circuit during a defect test (see fig. 8. Kim et al. show testing transistor M6. If there is a broken connection in CP1 no current will flow). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH R HALEY/ Primary Examiner, Art Unit 2621
Read full office action

Prosecution Timeline

Apr 01, 2025
Application Filed
Feb 17, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
86%
With Interview (+6.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1114 resolved cases by this examiner. Grant probability derived from career allow rate.

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