Prosecution Insights
Last updated: August 17, 2026
Application No. 19/096,997

DISPLAY PANEL INCLUDING TEST TRANSISTOR AND DEFECT DETECTION METHOD FOR DISPLAY PANEL

Final Rejection §103
Filed
Apr 01, 2025
Priority
Dec 23, 2022 — RE 10-2022-0183116 +1 more
Examiner
HALEY, JOSEPH R
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
1y 0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
897 granted / 1133 resolved
+17.2% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
27 currently pending
Career history
1165
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
57.5%
+17.5% vs TC avg
§102
23.9%
-16.1% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1133 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2 and 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2020/0302840) in view of Cho et al. (US 2019/0392741). In regard to claim 1, Kim et al. teach a display panel comprising: a display panel (fig. 1A) comprising: a plurality of pixel circuits configured to drive a plurality of inorganic light-emitting elements (fig. 1B and paragraph 106); a plurality of pixel electrodes configured to connect the plurality of inorganic light-emitting elements to the plurality of pixel circuits (fig. 14 CP1 and paragraph 236. Kim et al. shows the anode is connected to M6, M7 and M8 through CP1), each of the plurality of pixel electrodes comprising an anode pad (fig. 12 AE and CNT3); a plurality of test transistors connected to the plurality of pixel circuits through the plurality of pixel electrodes (M8 connected to CP1 through BRP 4 and 5); and at least one processor (paragraph 80) configured to: transmit data signals (see data driver 300); detect whether at least one of the plurality of pixel electrodes is defective based on the received current (fig. 8 and fig. 14 CP1. If the pixel electrode CP1 is defective no current will flow through the test transistor and will register as defective) but does not specifically teach an inspection device connected to the display panel, the inspection device comprising an interface connected to the plurality of test transistors through detection wiring; transmit and control signals to the display panel through the interface for a defect test of at least one of the plurality of pixel circuits; receive, through the interface, a signal from one of the plurality of test transistors via the detection wiring (paragraph 96 of Kim et al. show a test device but not the interface and detection wiring). Cho et al. teach an inspection device connected to the display panel (element 130), the inspection device comprising an interface connected to the plurality of test transistors through detection wiring (element 310); transmit control signals to the display panel through the interface for a defect test of at least one of the plurality of pixel circuits (elements 320, fig. 9 and paragraph 63); receive, through the interface, a signal from one of the plurality of test transistors via the detection wiring (paragraph 64, Cho et al. teach sensing a voltage). The two are analogous art because they both deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kim et al. with the separate inspection device of Cho et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kim et al. with the separate inspection device of Cho et al. because the inspection device of Cho et al. would work equally as well in the apparatus of Kim et al. as it does separately. One of ordinary skill in the art would recognize the inspection device of Cho et al. would provide predictable results and making the inspection device separate would allow for the simplification of the circuitry of each device. In regard to claims 2 and 10, Kim et al. teach a plurality of metal layers comprising: a first metal layer and a second metal layer on which the plurality of pixel circuits and the plurality of test transistors are formed (fig. 15 ACT1, ACT2 and GE); a third metal layer on which a driving electrode for supplying a driving voltage to the plurality of pixel circuits is formed (fig. 15 layer VIA2, PL1 and paragraph 114); and a fourth metal layer on which a ground electrode for supplying a ground voltage to the plurality of pixel circuits is formed, and wherein the plurality of pixel electrodes are formed on the fourth metal layer (fig. 15, PL2. The electrode CP1 is connected to AE via a metal layer on the layer including PL2. The via and the electrode CP1 are a single element). Claim 7 is the method corresponding to the apparatus of claim 1 and is rejected on the same grounds. In regard to claim 8, Kim et al. teach wherein each of the plurality of pixel electrodes comprise an anode pad to which a test transistor of the plurality of test transistors is connected (CP1), and wherein the detecting comprises, based on no current flowing through the test transistor according to the voltage, detecting that the anode pad is defective (figs. 8 and 14. If CP1 is broken no current will flow through the test transistor). In regard to claim 9, Kim et al. teach wherein, based on the anode pad being opened or a connection wiring between a pixel circuit of the plurality of pixel circuits and the anode pad through a via being disconnected, no current flows through the test transistor in a state in which the voltage is applied to the pixel circuit during the defect test of at least one of the plurality of pixel circuits (figs. 8 and 14. If CP1 is broken no current will flow through the test transistor). Claim(s) 3-6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Cho et al. further considered with Zhao (US 2024/0040865). In regard to claim 3, Kim et al. and Cho et al. teach all the elements of claim 3 except wherein each of the plurality of pixel electrodes comprise: a cathode pad connected to the ground electrode; and an anode pad connected to a pixel circuit of the plurality of pixel circuits. Zhao teaches wherein each of the plurality of pixel electrodes comprise: a cathode pad connected to the ground electrode (fig. 3 element 284 is connected to element 33), and wherein the anode pad is connected to a pixel circuit of the plurality of pixel circuits (element 282 is connected to elements T1, T3 and 311). The three are analogous art because they all deal with the same field of invention of displays. Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kim et al. and Cho et al. with the connections of Zhao. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kim et al. and Cho et al. with the connections of Zhao because the connections of Zhao would work equally as well in the apparatus of Kim et al. and Cho et al. as they do separately. One of ordinary skill in the art would recognize the connections of Zhao would provide predictable results and would improve manufacturing efficiency. In regard to claims 4 and 11, Zhao teaches wherein the pixel circuit of the plurality of pixel circuits is connected to the anode pad through a first via (fig. 3, T1 is connected to element 282 and the anode through via K5); and wherein a test transistor of the plurality of test transistors is connected to the anode pad through a second via (elements K4 and T3). In regard to claim 5, Zhao teaches wherein the plurality of inorganic light-emitting elements are mounted on the display panel such that a cathode terminal of each of the plurality of inorganic light-emitting elements is connected to the cathode pad (fig. 3 element 33 is connected to element 284) and an anode terminal of each of the plurality of inorganic light-emitting elements is connected to the anode pad (element 282 is connected to element 311). In regard to claims 6, Kim et al. teach wherein, based on the anode pad being opened or a connection wiring between the pixel circuit and the anode pad through the first via being disconnected, no current flows through the test transistor in a state in which a voltage is applied to the pixel circuit during the defect test of the at least one of the plurality of pixel circuits (see fig. 8. Kim et al. show testing transistor M6. If there is a broken connection in CP1 no current will flow). Allowable Subject Matter Claims 12-19 are allowed. The following is an examiner’s statement of reasons for allowance: In regard to claims 12 and 16, the prior art fails to teach or make obvious the anode pad being on the same layer as the pixel electrodes, the first and second vias in combination with the claim’s other features. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH R HALEY/ Primary Examiner, Art Unit 2621
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Prosecution Timeline

Apr 01, 2025
Application Filed
Feb 25, 2026
Non-Final Rejection mailed — §103
Apr 17, 2026
Interview Requested
Apr 27, 2026
Applicant Interview (Telephonic)
Apr 28, 2026
Examiner Interview Summary
May 22, 2026
Response Filed
Jul 27, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
86%
With Interview (+7.2%)
2y 5m (~1y 0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1133 resolved cases by this examiner. Grant probability derived from career allowance rate.

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