DETAILED ACTION
This Office Action, based on application 19/097,029 filed 1 April 2025, is filed
responsive to applicant’s initial filing of the application. Claims 1-20, as originally filed, are
currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 4-7, 12-15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over DEWITT JR et al (US PGPub 2003/0135789) in further view of NEWMAN et al (US Patent 5,301,288).
With respect to Claim 1, DEWITT discloses a system comprising:
a memory device (Fig 1B – Local Memory 124; Fig 1H – Physical Memory 186) comprising a first portion addressable by a first portion of physical addresses of the memory device, and a second portion addressable by a first portion of virtual addresses of a plurality of virtual addresses, wherein the first portion of virtual addresses maps to a second portion of physical addresses of the memory device (¶[0056-0062]; Fig 1H illustrates an allocation map of physical memory 186 including portions that are {e.g. Data[1] 194} and are not {e.g. Kernel 187} addressable via virtual memory for an application); and
a processing device operatively coupled to the memory device (Fig 1B, Processor Card 111 is coupled to Memory Card 123 comprising Local Memory 124 via Bus 115), the processing device to perform operations comprising:
receiving a first request for a first assignment of memory addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system”);
determining, based on the first request, whether to assign a first set of physical addresses for the first assignment of memory addresses from the first portion of physical addresses (¶[0083] – “in some cases in which the application program has the appropriate privileges {similar to ‘determining … whether to assign a first set of physical addresses …’}, the application can request that the memory block be allocated in physical memory such that the application is given a physical address pointer to the memory block”);
responsive to determining not to assign the first set of physical addresses from the first portion of physical addresses, requesting a first set of virtual addresses of the plurality of virtual addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system, and the operating system provides a memory block to the application in the form of a pointer to the memory block within the application’s virtual address space”).
DEWITT may not explicitly disclose wherein the plurality of virtual addresses are contiguous virtual addresses, and storing first data to a second set of physical addresses contiguously mapped to the first set of virtual addresses.
However, NEWMAN discloses wherein the plurality of virtual addresses are contiguous virtual addresses (Col 12, Lines 54-59 – “the address space allocation module 16, in step 111, locates a contiguous portion of virtual address space for the process 12 of the application program 11 … and allocates a group of one or more tile table entries therefor”), and storing first data to a second set of physical addresses contiguously mapped to the first set of virtual addresses (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 … to store processed data in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
DEWITT and NEWMAN are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT and NEWMAN before him or her, to modify the memory allocation procedure of DEWITT to include allocating virtual addresses contiguously as taught by NEWMAN. A motivation for doing so would have been to facilitate translation of virtual addresses of array data to physical addresses thereby increasing the efficiency of data storage and retrieval in the virtual memory (Col 3, Lines 52-65). Therefore, it would have been obvious to combine DEWITT and NEWMAN to obtain the invention as specified in the instant claims.
With respect to Claim 13, DEWITT discloses a method comprising:
receiving a first request for a first assignment of memory addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system”);
determining, based on the first request, whether to assign a first set of physical addresses for the first assignment of memory addresses from a first portion of physical addresses of a memory device, wherein a second portion of physical addresses of the memory device maps to virtual addresses of a plurality of virtual addresses (¶[0083] – “in some cases in which the application program has the appropriate privileges {similar to ‘determining … whether to assign a first set of physical addresses …’}, the application can request that the memory block be allocated in physical memory such that the application is given a physical address pointer to the memory block”);
responsive to determining not to assign the first set of physical addresses from the first portion of physical addresses, requesting a first set of virtual addresses of the plurality of virtual addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system, and the operating system provides a memory block to the application in the form of a pointer to the memory block within the application’s virtual address space”).
DEWITT may not explicitly disclose wherein the plurality of virtual addresses are contiguous virtual addresses, and storing data to a second set of physical addresses contiguously mapped to the first set of virtual addresses.
However, NEWMAN discloses wherein the plurality of virtual addresses are contiguous virtual addresses (Col 12, Lines 54-59 – “the address space allocation module 16, in step 111, locates a contiguous portion of virtual address space for the process 12 of the application program 11 … and allocates a group of one or more tile table entries therefor”), and storing data to a second set of physical addresses contiguously mapped to the first set of virtual addresses (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 … to store processed data in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
DEWITT and NEWMAN are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT and NEWMAN before him or her, to modify the memory allocation procedure of DEWITT to include allocating virtual addresses contiguously as taught by NEWMAN. A motivation for doing so would have been to facilitate translation of virtual addresses of array data to physical addresses thereby increasing the efficiency of data storage and retrieval in the virtual memory (Col 3, Lines 52-65). Therefore, it would have been obvious to combine DEWITT and NEWMAN to obtain the invention as specified in the instant claims.
With respect to Claim 18, DEWITT discloses a computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory device comprising a plurality of memory cells, cause the controller to perform operations comprising:
receiving a first request for a first assignment of memory addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system”);
determining, based on the first request, whether to assign a first set of physical addresses for the first assignment of memory addresses from a first portion of physical addresses of a memory device, wherein a second portion of physical addresses of the memory device maps to virtual addresses of a plurality of virtual addresses (¶[0083] – “in some cases in which the application program has the appropriate privileges {similar to ‘determining … whether to assign a first set of physical addresses …’}, the application can request that the memory block be allocated in physical memory such that the application is given a physical address pointer to the memory block”);
responsive to determining not to assign the first set of physical addresses from the first portion of physical addresses, requesting a first set of virtual addresses of the plurality of virtual addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system, and the operating system provides a memory block to the application in the form of a pointer to the memory block within the application’s virtual address space”).
DEWITT may not explicitly disclose wherein the plurality of virtual addresses are contiguous virtual addresses, and storing first data to a second set of physical addresses contiguously mapped to the first set of virtual addresses.
However, NEWMAN discloses wherein the plurality of virtual addresses are contiguous virtual addresses (Col 12, Lines 54-59 – “the address space allocation module 16, in step 111, locates a contiguous portion of virtual address space for the process 12 of the application program 11 … and allocates a group of one or more tile table entries therefor”), and storing first data to a second set of physical addresses contiguously mapped to the first set of virtual addresses (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 … to store processed data in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
DEWITT and NEWMAN are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT and NEWMAN before him or her, to modify the memory allocation procedure of DEWITT to include allocating virtual addresses contiguously as taught by NEWMAN. A motivation for doing so would have been to facilitate translation of virtual addresses of array data to physical addresses thereby increasing the efficiency of data storage and retrieval in the virtual memory (Col 3, Lines 52-65). Therefore, it would have been obvious to combine DEWITT and NEWMAN to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of DEWITT and NEWMAN disclose the system of claim 1.
NEWMAN further discloses wherein the second set of physical addresses comprise physical addresses of the second portion of physical addresses of the memory device (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 … to store processed data in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
With respect to Claim 6, the combination of DEWITT and NEWMAN disclose the system of claim 1.
DEWITT further discloses the operations further comprising: receiving a second request for a second set of memory addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system”); determining, based on the second request, to request a second set of virtual addresses of the plurality of contiguous virtual addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system, and the operating system provides a memory block to the application in the form of a pointer to the memory block within the application’s virtual address space”).
NEWMAN further discloses the operations further comprising: storing data to a third set of physical addresses contiguously mapped to the second set of virtual addresses (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 … to store processed data in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
With respect to Claim 7, the combination of DEWITT and NEWMAN disclose the system of claim 6.
DEWITT further discloses wherein the first request and the second request pertain to a first application of the system (¶[0083] – “the application program can generate a memory allocation request to the operating system”).
With respect to Claim 12, the combination of DEWITT and NEWMAN disclose the system of claim 1.
DEWITT further discloses wherein the memory device is a cache coupled to a compute unit (Fig 1H, Processor Card 116 is coupled to Memory Card 123), wherein the cache comprises instruction sets for the compute unit (Fig 1H, e.g. Application Program [1] 192).
With respect to Claim 14, the combination of DEWITT and NEWMAN disclose the method of claim 13.
NEWMAN further discloses wherein the second set of physical addresses comprise physical addresses of the second portion of physical addresses of the memory device (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 … to store processed data in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
With respect to Claim 15, the combination of DEWITT and NEWMAN disclose the method of claim 13.
DEWITT further discloses receiving a second request for a second set of memory addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system”); determining, based on the second request, to request a second set of virtual addresses of the plurality of contiguous virtual addresses (¶[0083] – “the application program can generate a memory allocation request to the operating system, and the operating system provides a memory block to the application in the form of a pointer to the memory block within the application’s virtual address space”).
NEWMAN further discloses storing data to a third set of physical addresses contiguously mapped to the second set of virtual addresses (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 … to store processed data in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
Claim(s) 3-5, 8-11, 16, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over DEWITT JR in further view of NEWMAN and PEINADO et al (US PGPub 2003/0200412).
With respect to Claim 3, the combination of DEWITT and NEWMAN disclose the system of claim 2.
NEWMAN further discloses the operations further comprising: receiving a request to access the first data stored at physical addresses of the memory device; determining, based on the request, that the first data is addressable by the first set of virtual addresses; and processing the request using the second set of physical addresses (Col 4, Lines 30-50 – “One type of memory management request enables the application program … to access a physical memory 13 to retrieve data from … in storage locations in the memory. In this type of memory management request, the application program provides a … virtual address, which identifies a virtual storage location in its virtual address space … the address translation module … performs a translation operation to map the … virtual address from the application program to a … physical address which is used in accessing the physical memory.”).
DEWITT and NEWMAN may not explicitly disclose the operations further comprising: determining, based on the request, that the first data is addressable by the first set of virtual addresses.
However, PEINADO discloses the operations further comprising: determining, based on the request, that the first data is addressable by the first set of virtual addresses (¶[0121] – “guard 206(1) receives a request to access a resource … a type 1 request identifies a resource by its virtual address, and a type 2 requests <sic> identifies a resource by its physical address… Guard 206(1) determines whether the request is of type 1 or type 2.”).
DEWITT, NEWMAN, and PEINADO are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT, NEWMAN, and PEINADO before him or her, to modify memory access requests of the combination of DEWITT and NEWMAN to include different types of requests that may access the memory using different types of addresses as taught by PEINADO. A motivation for doing so would have been to expedite the processing of certain types of access requests since certain types of access requests may be evaluated more efficiently based on policy (¶[0008-0011]). Therefore, it would have been obvious to combine DEWITT, NEWMAN, and PEINADO to obtain the invention as specified in the instant claims.
With respect to Claim 4, the combination of DEWITT, NEWMAN, and PEINADO disclose the system of claim 3.
PEINADO further discloses wherein determining that the first data is addressable by the first set of physical addresses comprises: determining that a value of set bit of an address of the request indicates the first data is addressable by virtual addresses (¶[0121] – “Guard 206(1) determines whether the request is of type 1 or type 2.”).
With respect to Claim 5, the combination of DEWITT, NEWMAN, and PEINADO disclose the system of claim 3.
DEWITT further discloses the operations further comprising: determining that an address of the request is within an address range indicating the data is addressable by virtual addresses (¶[0086] – “An operating system can pin the virtual memory pages that are within a specified address range in an application program's address space. Pinning a memory region prohibits the operating system's paging mechanism from paging out the real memory pages that are backing the pinned memory region. Once the memory region is pinned, any access to that memory region cannot result in a page fault, thereby preventing interrupts that accompany page faults”).
With respect to Claim 8, the combination of DEWITT and NEWMAN disclose the system of claim 6.
DEWITT and NEWMAN may not explicitly disclose wherein the first request pertains to a first application of the system, and the second request pertains to a second application of the system.
However, PEINADO discloses wherein the first request pertains to a first application of the system, and the second request pertains to a second application of the system (¶[0005] – “most modern operating systems implement the concept of an ‘address space’, where each process is assigned (generally on a continually-changing basis) certain pages or segments of physical memory that the process can access through it’s virtual memory mappings, and where a process cannot access pages (or segments) that are in another process’s address space”).
DEWITT, NEWMAN, and PEINADO are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT, NEWMAN, and PEINADO before him or her, to modify memory access requests of the combination of DEWITT and NEWMAN to include separate address spaces for different applications as taught by PEINADO. A motivation for doing so would have been to prevent unauthorized access requests and prevent memory corruption (¶[0006]). Therefore, it would have been obvious to combine DEWITT, NEWMAN, and PEINADO to obtain the invention as specified in the instant claims.
With respect to Claim 9, the combination of DEWITT and NEWMAN disclose the system of claim 1.
DEWITT and NEWMAN may not explicitly disclose the operations further comprising: responsive to determining to assign the first set of physical addresses, storing the first data to the first set of physical addresses.
However, PEINADO discloses the operations further comprising: responsive to determining to assign the first set of physical addresses, storing the first data to the first set of physical addresses (¶[0121] – “guard 206(1) receives a request to access a resource … a type 1 request identifies a resource by its virtual address, and a type 2 requests <sic> identifies a resource by its physical address… Guard 206(1) determines whether the request is of type 1 or type 2.”. Fig 18, Step 1824 illustrates a type 2 write request may be allowed).
DEWITT, NEWMAN, and PEINADO are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT, NEWMAN, and PEINADO before him or her, to modify memory access requests of the combination of DEWITT and NEWMAN to include different types of requests that may access the memory using different types of addresses as taught by PEINADO. A motivation for doing so would have been to expedite the processing of certain types of access requests since certain types of access requests may be evaluated more efficiently based on policy (¶[0008-0011]). Therefore, it would have been obvious to combine DEWITT, NEWMAN, and PEINADO to obtain the invention as specified in the instant claims.
With respect to Claim 10, the combination of DEWITT, NEWMAN, and PEINADO disclose the system of claim 9.
PEINADO further discloses wherein the plurality of contiguous virtual addresses are stored in a global address translation table (¶[0113] – “the contents of MP(s) {mapped pages} is defined by address translation tables”), wherein the operations further comprise: sending an indication to update the global address translation table to reflect that the first set of physical addresses are assigned as the first assignment of memory addresses (¶[0078] – “the memory maps elements of A to elements of M, since the memory defines, at any given moment in time, which element of M corresponds to a particular element of A. Furthermore, the mapping is "modifiable" in the sense that it can be changed by writing new values to the memory”).
With respect to Claim 11, the combination of DEWITT, NEWMAN, and PEINADO disclose the system of claim 10.
NEWMAN further discloses a data structure comprising an address table Fig 1 – tile table 15), wherein entries of the address table indicate a virtual address of the plurality of contiguous virtual addresses and a corresponding physical address that is contiguously mapped to the virtual address (Col 5, Lines 29-33 – “it establishes entries in the tile table 15 which enable the address translation module 14 to generate physical addresses in response to virtual addresses from the applications program 11 for the portion of the process's virtual address space allocated to the image”), wherein the data structure further comprises a bit mask vector, wherein each entry of the bit mask vector indicates whether a respective set of virtual addresses of the plurality of contiguous virtual addresses are assigned as an assignment of memory addresses (Fig 2C – Valid Flags 53 – Col 9, Lines 18-21 – “A valid flag 53 indicates whether the tile table entry 50 is valid, that is, if the address translation module 14 can use it in performing a translation operation”).
With respect to Claim 16, the combination of DEWITT and NEWMAN disclose the method of claim 13.
DEWITT and NEWMAN may not explicitly disclose responsive to determining to assign the first set of physical addresses, storing the data to the first set of physical addresses.
However, PEINADO discloses responsive to determining to assign the first set of physical addresses, storing the data to the first set of physical addresses (¶[0121] – “guard 206(1) receives a request to access a resource … a type 1 request identifies a resource by its virtual address, and a type 2 requests <sic> identifies a resource by its physical address… Guard 206(1) determines whether the request is of type 1 or type 2.”. Fig 18, Step 1824 illustrates a type 2 write request may be allowed).
DEWITT, NEWMAN, and PEINADO are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT, NEWMAN, and PEINADO before him or her, to modify memory access requests of the combination of DEWITT and NEWMAN to include different types of requests that may access the memory using different types of addresses as taught by PEINADO. A motivation for doing so would have been to expedite the processing of certain types of access requests since certain types of access requests may be evaluated more efficiently based on policy (¶[0008-0011]). Therefore, it would have been obvious to combine DEWITT, NEWMAN, and PEINADO to obtain the invention as specified in the instant claims.
With respect to Claim 17, the combination of DEWITT, NEWMAN, and PEINADO disclose the method of claim 16.
PEINADO further discloses wherein the plurality of contiguous virtual addresses are stored in a global address translation table (¶[0113] – “the contents of MP(s) {mapped pages} is defined by address translation tables”), the method further comprising: sending an indication to update the global address translation table to reflect that the first set of physical addresses are assigned as the first assignment of memory addresses (¶[0078] – “the memory maps elements of A to elements of M, since the memory defines, at any given moment in time, which element of M corresponds to a particular element of A. Furthermore, the mapping is "modifiable" in the sense that it can be changed by writing new values to the memory”).
With respect to Claim 19, the combination of DEWITT and NEWMAN disclose the computer-readable non-transitory storage medium of claim 18.
DEWITT and NEWMAN may not explicitly disclose the operations further comprising: responsive to determining to assign the first set of physical addresses, storing the data to the first set of physical addresses.
However, PEINADO discloses the operations further comprising: responsive to determining to assign the first set of physical addresses, storing the data to the first set of physical addresses (¶[0121] – “guard 206(1) receives a request to access a resource … a type 1 request identifies a resource by its virtual address, and a type 2 requests <sic> identifies a resource by its physical address… Guard 206(1) determines whether the request is of type 1 or type 2.”. Fig 18, Step 1824 illustrates a type 2 write request may be allowed).
DEWITT, NEWMAN, and PEINADO are analogous art because they are from the same field of endeavor of memory management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of DEWITT, NEWMAN, and PEINADO before him or her, to modify memory access requests of the combination of DEWITT and NEWMAN to include different types of requests that may access the memory using different types of addresses as taught by PEINADO. A motivation for doing so would have been to expedite the processing of certain types of access requests since certain types of access requests may be evaluated more efficiently based on policy (¶[0008-0011]). Therefore, it would have been obvious to combine DEWITT, NEWMAN, and PEINADO to obtain the invention as specified in the instant claims.
With respect to Claim 20, the combination of DEWITT, NEWMAN, and PEINADO disclose the computer-readable non-transitory storage medium of claim 19.
PEINADO further discloses wherein the plurality of contiguous virtual addresses are stored in a global address translation table (¶[0113] – “the contents of MP(s) {mapped pages} is defined by address translation tables”), the operations further comprising: sending an indication to update the global address translation table to reflect that the first set of physical addresses are assigned as the first assignment of memory addresses (¶[0078] – “the memory maps elements of A to elements of M, since the memory defines, at any given moment in time, which element of M corresponds to a particular element of A. Furthermore, the mapping is "modifiable" in the sense that it can be changed by writing new values to the memory”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure teach similar processes for allocating memory for access via physical or virtual addressing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T LOONAN whose telephone number is (571)272-6994. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T LOONAN/Primary Examiner, Art Unit 2137
Prosecution Insights