DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The double patenting rejection has been withdrawn in view of amendments to the claims.
Response to Arguments
Applicant's arguments filed August 13, 2026 have been fully considered but they are not persuasive.
Regarding the rejections under 35 U.S.C. § 103, Applicant first argues, “Huang does not teach or suggest the claimed system that performs concurrent erase operations on ‘a first set of memory cells of the first memory block of the first plane and a second set of memory cells of the second memory block of a second memory plane,’ as received in amended claim 1.”
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant’s arguments with regard to Huang do not apply to the combination of Huang with Yi that the rejection relies upon. In particular, Examiner has relied upon Yi as disclosing concurrently erasing a first set of memory cells of a first memory block and a second set of memory cells of a second memory block by applying erase pulses (see paragraph 56 of Yi, erase operations are performed on multiple blocks by applying erase voltages at the same time). Huang is relied upon for the teaching of erase verification in two stages. Although Huang teaches performing an erase verification only on one set of cells in one block, a person of ordinary skill in the art would have found it obvious to combine Huang with the teaching of Yi to apply the erase verification to multiple sets of cells in multiple blocks in order to facilitate faster erasing and verification of multiple memory blocks.
Applicant also argues that Huang does not disclose a distinct “first stage” and “second stage” erase verification. Examiner respectfully disagrees. Huang discloses performing erase verification at a first erase verify level EV+ (see fig. 8, s806 and paragraph 60 of Huang). This is commensurate with the claimed “first stage” erase verification where the first threshold voltage distribution level of the first memory block and the second threshold voltage distribution level of the second memory block are verified to be less than a first erase verify threshold voltage level. Huang then teaches performing another erase verify at erase verify level EV (see fig. 8, s812 and paragraph 61 of Huang) wherein the first set of threshold voltages of the first block and the second set of threshold voltages of the second block are verified to be less than a final erase verify threshold voltage. EV is less than EV+ (see paragraph 56 of Huang).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7, 9-10, 12-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPub 2018/0102172 to Yi in view of US PGPub 2022/0223210 to Huang and further in view of US PGPub 2018/0203774 to Srinivasan et al. (“Srinivasan”).
Regarding claim 1, Yi discloses a system comprising:
a memory device (memory device 150, see fig. 1); and
a processing device, operatively coupled with the memory device (controller 130, see fig. 1), to perform operations comprising:
causing, during a first stage of an erase operation, one or more erase pulses of the erase operation to be applied to a first set of memory cells of a first memory block and a second set of memory cells of a second memory blocks concurrently (see paragraph 56, erase is performed for multiple blocks by applying erase voltages at the same time);
causing, during the first stage of the erase operation, one or more first erase verify sub-operations of the erase operation to be performed to verify a first memory block is erased (see paragraph 56, after performing the erase operation, the memory device may perform erase verification for each block);
causing, during the first stage of the erase operation, one or more second erase verify sub-operations of the erase operation to be performed to verify a second memory block is erased (see paragraph 56, after performing the erase operation, the memory device may perform erase verification for each block).
Yi does not disclose performing erase verification by verifying a first threshold voltage distribution of a first set of threshold voltages associated with the first set of memory cells and a second threshold voltage distribution associated with the second set of memory cells is less than an erase verify threshold voltage level. Yi also does not disclose a second stage erase operation with one or more third erase verify sub-operations to verify that the first set of memory cells and the second set of memory cells are erased, wherein the one or more third erase verify sub-operations comprise determining each threshold voltage of the first set of threshold voltages associated with the first set of memory cells and the second set of threshold voltages associated with the second set of memory cells is less than a final erase verify threshold voltage level, and wherein the final erase verify threshold voltage level is less than the first erase verify threshold voltage level. Huang discloses a memory system performing erase verification by testing whether the threshold voltages of the memory cells are below an erase verify level EV (see paragraphs 46 and 49 and fig. 5 of Huang). Huang also discloses performing erase verification in multiple stages (see fig. 8 and paragraph 61, after the cells pass erase verification at EV+, they are erase verified at EV). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to combine the erase verification method of Huang with the memory system of Yi in order to optimize the erasure and verification of the memory cells.
Yi and Huang do not disclose wherein the first memory block is located in a first memory plane and the second memory block is located in a second memory plane. Srinivasan discloses applying a multi-plane storage operation including simultaneously erasing multiple blocks belonging to different planes (see paragraph 6 of Srinivasan). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to apply the multiple erasure of Yi to blocks on different planes so that blocks on different planes can be concurrently erased to reduce operational latency.
Regarding claim 2, Yi discloses the system wherein the operations further comprising issuing a first command to identify first address information associated with the first set of memory cells of the first memory block and second address information associated with the second set of memory cells of the second memory block (see paragraph 58 of Yi, a multi-block erase command precedes address information identifying the blocks to be erased).
Regarding claim 3, Yi discloses the system wherein the operations further comprise issuing a second command to cause sending of the first address information and the second address information to the memory device (see paragraph 59 of Yi, the last block erase information is ended with an erase confirm command before the memory device performs the erase on the selected blocks).
Regarding claim 4, Huang discloses the erase operation comprises a pre-program sub-operation comprising applying one or more pre-program pulses to one or more wordlines associated with the first set of memory cells and the second set of memory cells (see fig. 8 and paragraph 59 of Huang). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to use the preprogramming of Huang in order to narrow the distribution of threshold voltages of the memory cells.
Regarding claims 5 and 6, Huang discloses the one or more erase pulses causes a first source voltage associated with the first memory block and a second source voltage associated with the second memory block to be ramped to the erase voltage level (see paragraph 47 of Huang). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to use the incremental step pulse erase of Huang in order to fully ensure erasing of the cells.
Regarding claim 7, the combination of references renders obvious the system, wherein the one or more first erase verify sub-operations comprise determining a first voltage of the first set of memory cells of the first memory block are less than an erase threshold voltage level (see paragraphs 46 and 49 and fig. 5 of Huang).
Regarding claim 10, Yi discloses a system comprising:
a memory device (memory device 150, see fig. 1); and
a processing device, operatively coupled with the memory device (controller 130, see fig. 1), to perform operations comprising:
identifying a command to execute an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block (see paragraphs 54 and 55, two blocks can be selected for erasing);
causing each erase pulse of a set of erase pulses of the erase operation to be applied concurrently to the first set of memory cells of the first memory block and the second set of memory cells of the second memory blocks (see paragraph 56, erase is performed for multiple blocks by applying erase voltages at the same time);
causing execution of one or more first erase verify sub-operations to verify the first set of memory cells is erased (see paragraph 56, after performing the erase operation, the memory device may perform erase verification for each block);
causing execution of one or more second erase verify sub-operations to verify the second set of memory cells is erased (see paragraph 56, after performing the erase operation, the memory device may perform erase verification for each block).
Yi does not disclose performing erase verification by verifying a first threshold voltage distribution of a first set of threshold voltages associated with the first set of memory cells and a second threshold voltage distribution associated with the second set of memory cells is less than an erase verify threshold voltage level. Yi also does not disclose a second stage erase operation with one or more third erase verify sub-operations to verify that the first set of memory cells and the second set of memory cells are erased, wherein the one or more third erase verify sub-operations comprise determining each threshold voltage of the first set of threshold voltages associated with the first set of memory cells and the second set of threshold voltages associated with the second set of memory cells is less than a final erase verify threshold voltage level, and wherein the final erase verify threshold voltage level is less than the first erase verify threshold voltage level. Huang discloses a memory system performing erase verification by testing whether the threshold voltages of the memory cells are below an erase verify level EV (see paragraphs 46 and 49 and fig. 5 of Huang). Huang also discloses performing erase verification in multiple stages (see fig. 8 and paragraph 61, after the cells pass erase verification at EV+, they are erase verified at EV). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to combine the erase verification method of Huang with the memory system of Yi in order to optimize the erasure and verification of the memory cells.
Yi and Huang do not disclose wherein the first memory block is located in a first memory plane and the second memory block is located in a second memory plane. Srinivasan discloses applying a multi-plane storage operation including simultaneously erasing multiple blocks belonging to different planes (see paragraph 6 of Srinivasan). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to apply the multiple erasure of Yi to blocks on different planes so that blocks on different planes can be concurrently erased to reduce operational latency.
Regarding claim 12, Yi discloses the system wherein the command comprises a first address information associated with the first set of memory cells of the first memory block and second address information associated with the second set of memory cells of the second memory block (see paragraph 58 of Yi, a multi-block erase command precedes address information identifying the blocks to be erased).
Regarding claim 13, Huang discloses a memory system performing erase verification by testing whether the threshold voltages of the memory cells are below an erase verify level EV (see paragraphs 46 and 49 and fig. 5 of Huang). Huang also discloses performing erase verification in multiple stages (see fig. 8 and paragraph 61, after the cells pass erase verification at EV+, they are erase verified at EV). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to combine the erase verification method of Huang with the memory system of Yi in order to optimize the erasure and verification of the memory cells.
Regarding claims 14 and 15, Huang discloses the set of erase pulses cause a first source voltage associated with the first memory block and the second voltage associated with the second memory block to be ramped to the erased voltage level (see paragraph 47 of Huang). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to use the incremental step pulse erase of Huang in order to fully ensure erasing of the cells.
Regarding claim 16, Huang discloses a system comprising:
a memory device (memory device 150, see fig. 1); and
a processing device, operatively coupled with the memory device (controller 130, see fig. 1), to perform operations comprising:
causing each erase pulse of a set of erase pulses of the erase operation to be applied concurrently to the first set of memory cells of the first memory block and the second set of memory cells of the second memory blocks (see paragraph 56, erase is performed for multiple blocks by applying erase voltages at the same time);
causing execution of one or more erase verify sub-operations of the erase operation to verify the first set of memory cells and the second set of memory cells are erased (see paragraph 56, after performing the erase operation, the memory device may perform erase verification for each block).
Yi does not disclose performing erase verification by verifying each threshold voltage of a first set of threshold voltages associated with the first set of memory cells and a second set of threshold voltages associated with the second set of memory cells is less than an erase verify threshold voltage level. Yi also does not disclose a second stage erase operation with one or more third erase verify sub-operations to verify that the first set of memory cells and the second set of memory cells are erased. Huang discloses a memory system performing erase verification by testing whether the threshold voltages of the memory cells are below an erase verify level EV (see paragraphs 46 and 49 and fig. 5 of Huang). Huang also discloses performing erase verification in multiple stages (see fig. 8 and paragraph 61, after the cells pass erase verification at EV+, they are erase verified at EV). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to combine the erase verification method of Huang with the memory system of Yi in order to optimize the erasure and verification of the memory cells.
Yi and Huang do not disclose wherein the first memory block is located in a first memory plane and the second memory block is located in a second memory plane. Srinivasan discloses applying a multi-plane storage operation including simultaneously erasing multiple blocks belonging to different planes (see paragraph 6 of Srinivasan). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to apply the multiple erasure of Yi to blocks on different planes so that blocks on different planes can be concurrently erased to reduce operational latency.
Regarding claim 18, Yi discloses the system wherein the operations further comprising issuing a first command to identify first address information associated with the first set of memory cells of the first memory block and second address information associated with the second set of memory cells of the second memory block (see paragraph 58 of Yi, a multi-block erase command precedes address information identifying the blocks to be erased).
Regarding claim 19, Yi discloses the system wherein the operations further comprise providing the first address information and the second address information to the memory device (see paragraph 59 of Yi, the last block erase information is ended with an erase confirm command before the memory device performs the erase on the selected blocks).
Regarding claim 20, Huang discloses the erase operation comprises a pre-program sub-operation comprising applying one or more pre-program pulses to one or more wordlines associated with the first set of memory cells and the second set of memory cells (see fig. 8 and paragraph 59 of Huang). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to use the preprogramming of Huang in order to narrow the distribution of threshold voltages of the memory cells.
Claims 8, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yi in view of Huang and Srinivasan and further in view of US PGPub 2015/0348621 to Sako.
As applied in the rejections above, the combination of Yi, Huang, and Srinivasan renders obvious the systems for performing erase verification on memory blocks in two stages at two erase verification levels. The references do not disclose the final erase verify threshold voltage level is a negative voltage. Sako discloses using an erase verify voltage that has a negative value (see paragraph 40 of Sako). It would have been obvious at the time the application was filed to a person of ordinary skill in the art for the final erase verify threshold voltage level to be a negative voltage since using a negative erase verify voltage was known in the art to ensure the memory cell is fully erased.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D TSUI whose telephone number is (571)270-3253. The examiner can normally be reached Monday-Friday 8am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL D TSUI/Primary Examiner, Art Unit 2132
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