CTNF 19/097,425 CTNF 81026 DETAILED ACTION Claims 1-20 are pending. The office acknowledges the following papers: Abstract and remarks filed on 4/3/2025, Drawings filed on 6/9/2025, IDS filed on 12/19/2025. Priority The effective filing date for the subject matter defined in the pending claims in this application is 4/2/2024. Drawings The Examiner contends that the drawings submitted on 4/1/2025 are acceptable for examination proceedings. Specification 07-29 AIA The disclosure is objected to because of the following informalities: The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware. Published application paragraphs 224-232 include multiple drawing element citations to figure 17 that aren’t shown in figure 17. These are primarily elements labeled as various “3##” elements, but no “3##” elements exist in figure 17. These elements at first glance don’t appear to be within other drawings. Various other figures include similar incorrect data elements in the description . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-8 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Khailany et al. (U.S. 2022/0067530) . As per claim 1: Khailany disclosed a processing device having a plurality of processing lanes, the number of processing lanes being greater than a block size for an input block of a block-scaled input matrix (Khailany: Figures 1A-B, 2A, and 2C elements 105 and 120, paragraphs 31-32, 45, 62, and 76-77)(The vector MAC units (i.e. processing lanes) include multipliers are greater in size than an input vector size (i.e. block size), which is broadcasted to all vector MAC units for processing. Additionally, it would have been obvious to one of ordinary skill in the art that the number of vector MAC units is greater than the vector length of the input activation. In addition, according to “In re Japikse” (181 F.2d 1019, 86 USPQ 70 (CCPA 1950)), shifting the location of parts doesn’t give patentability over prior art.), the processing device configured to: receive an input block from the plurality of processing lanes (Khailany: Figures 1A-B elements 105, 120, and 135, paragraphs 31-32 and 45-49)(The input activation vector is broadcasted to vector MAC units (i.e. processing lanes). The multipliers within the vector MAC units receive the input activation vectors.); generate one or more input scale factors for the input block (Khailany: Figures 1B and 2B elements 137 and 235, paragraphs 48, 50, 56, and 66)(Scale factors are generated per input activation vector.); load a gains block of a block-scaled gains matrix and one or more gains scale factors (Khailany: Figures 1B and 2B-2C elements 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision based on a scale factor. The reduced weight vector and weight scale factor are loaded into each vector MAC unit for reuse. The set of reduced weight vectors sent to the set of vector MAC units reads upon the block-scaled gains matrix.); and generate result data scaled according to at least both the one or more input scale factors and the one or more gains scale factors by multiplying the input block and the gains block (Khailany: Figures 1B and 2C elements 120, 124-127 and 140, paragraphs 47-53, 76, and 78)(The vector MAC unit generates temporary result data for each input activation vector by performing a dot-product calculation and adjusting the product based on weight and input scale factors. The final product is accumulated through multiple calculation passes of different input activation vectors.). As per claim 2: Khailany disclosed the processing device of claim 1, wherein the processing device is further configured to: receive a plurality of input blocks and a plurality of input scale factors (Khailany: Figures 1A-B and 2C elements 105, 120, 135, and 2555, paragraphs 31-32, 45-49, 53, and 76)(The input activation vector and input scale factor are broadcasted to vector MAC units. Additionally, different input activation vectors and input scale factors are broadcasted to the vector MAC units over time.); load a plurality of gains blocks and a plurality of gains scale factors (Khailany: Figures 1B and 2B-2C elements 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision based on a scale factor. The reduced weight vector and weight scale factor are loaded into each vector MAC unit for reuse. The set of reduced weight vectors and weight scale factors sent to the set of vector MAC units reads upon the plurality of gains blocks and gains scale factors.); generate a plurality of result data blocks by multiplying respective input blocks of the plurality of input blocks and gains blocks of the plurality of gains blocks (Khailany: Figures 1B and 2C elements 120, 124-127 and 140, paragraphs 47-53, 76, and 78)(The vector MAC unit generates temporary result data for each input activation vector by performing a dot-product calculation and adjusting the product based on weight and input scale factors. The set of outputs by multiplier 127 reads upon the plurality of result data blocks.); and generate result data from the plurality of result data blocks (Khailany: Figures 1B and 2C elements 120, 124-127 and 140, paragraphs 47-53, 76, and 78)(The vector MAC unit generates temporary result data for each input activation vector by performing a dot-product calculation and adjusting the product based on weight and input scale factors. The final product is accumulated through multiple calculation passes of different input activation vectors.). As per claim 3: Khailany disclosed the processing device of claim 1, wherein: the processing device is further configured to generate the one or more input scale factors in a dense format and a replicated format (Khailany: Figures 1B and 2C elements 120 and 137, paragraphs 47-48, 76, and 78)(The input scale factor is broadcasted (i.e. copied) to the plurality of vector MAC units (i.e. processing lanes).), the dense format comprises a copy of the one or more input scale factors for each B processing lanes of the plurality of processing lanes, where B is equal to the block size of the input block (Khailany: Figures 1B and 2C elements 120 and 137, paragraphs 47-48, 76, and 78)(The input scale factor is broadcasted (i.e. copied) to the plurality of vector MAC units (i.e. processing lanes). Additionally, it would have been obvious to one of ordinary skill in the art that a subset of vector MAC units is equal to the vector length of the input activation. In addition, according to “In re Japikse” (181 F.2d 1019, 86 USPQ 70 (CCPA 1950)), shifting the location of parts doesn’t give patentability over prior art. Broadcasting the input scale factor to an equal number of vector MAC units as the vector length of the input activation (i.e. block size) reads upon the dense format.), and the replicated format comprises a copy of the one or more input scale factors for each processing lane of a group of B processing lanes (Khailany: Figures 1B and 2C elements 120 and 137, paragraphs 47-48, 76, and 78)(The input scale factor is broadcasted (i.e. copied) to the plurality of vector MAC units (i.e. processing lanes). This reads upon the replicated format.). As per claim 4: Khailany disclosed the processing device of claim 1, wherein the processing device is further configured to receive block-scaled data elements of the input block across multiple processing lanes (Khailany: Figures 1A-B elements 105, 120, 130-132, 135, 240, and 260, paragraphs 31-32, 45-49, 73, and 76-78)(The input activation vector is broadcasted to vector MAC units (i.e. processing lanes). The input activation vectors are scaled down to a reduced precision based on a scale factor. The multipliers within the vector MAC units receive the input activation vectors.) and the scale factor for the input block from one of the multiple processing lanes (Khailany: Figures 1A-B and 2C elements 105, 120-122, 135, and 2555, paragraphs 31-32, 45-49, 53, and 76)(The input scale factor is broadcasted to vector MAC units. Multiplier 122 of a given vector MAC unit receives the scale factor.). As per claim 5: Khailany disclosed the processing device of claim 1, wherein: at least one processing lane comprises a plurality of sub-lanes (Khailany: Figure 1B element 120, paragraphs 47-49)(A vector MAC unit includes a plurality of multipliers (i.e. sub-lanes) to multiply input activations and weights.), and in generating the input scale factor, the processing device is configured to: receive an un-scaled input block of un-scaled data elements (Khailany: Figures 1B and 2B-2C elements 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision based on a scale factor. The input activation vector prior to the reduction reads upon the un-scaled data elements.); and generate the input scale factor by performing a scale factor reduction on the un-scaled input block in a dimension corresponding to the plurality of sub-lanes (Khailany: Figures 1B and 2B-2C elements 105, 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision based on a scale factor. The input vector is along a dimension of the input activation tensor.). As per claim 6: Khailany disclosed the processing device of claim 5, wherein the un-scaled data elements comprise dynamic data (Khailany: Figures 1B and 2B-2C elements 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision based on a scale factor. The input activation vector prior to the reduction reads upon the un-scaled data elements. The input tensors are dynamically loaded data. The scale factors can be determined dynamically.) and the loaded gains block comprises static data (Khailany: Figures 1B and 2B-2C elements 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision based on a scale factor. The reduced weight vector and weight scale factor are loaded into each vector MAC unit for reuse. The set of reduced weight vectors sent to the set of vector MAC units reads upon the block-scaled gains matrix. The scale factors can be determined statically.). As per claim 7: Khailany disclosed the processing device of claim 1, wherein: at least one processing lane comprises a plurality of sub-lanes (Khailany: Figure 1B element 120, paragraphs 47-49)(A vector MAC unit includes a plurality of multipliers (i.e. sub-lanes) to multiply input activations and weights.), and the processing device is further configured to: receive un-scaled data elements (Khailany: Figures 1B and 2B-2C elements 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision based on a scale factor. The input activation vector prior to the reduction reads upon the un-scaled data elements.); and receive a target format for block-scaled data (Khailany: Paragraphs 24-25, 29, and 34-37)(Lower-precision formats can be selected based on target devices and applications.); transpose the un-scaled data elements from a dimension corresponding to the plurality of lanes to a dimension corresponding to the plurality of sub-lanes (Khailany: Figures 1B and 2B-2C elements 105, 120, 130-132, 240, and 260, paragraphs 47-48, 73, and 76-78)(The input and weight vectors are scaled down to a reduced precision (i.e. transpose) based on a scale factor. The input and weight vectors are along a dimension of the input activation and weight tensors. The reduced elements within the vectors are sent to multipliers (i.e. sub-lanes) within the vector MAC unit.). determine a maximum-valued or maximum-absolute-valued data element of the un-scaled data elements (Khailany: Paragraphs 39)(Scale factors are chosen based on a maximum absolute value of the initial higher-precision format.); and determine a scale factor for the maximum-valued or maximum-absolute- valued data element to divide the un-scaled data elements into a block-scaled element within the target format (Khailany: Paragraphs 39 and 47)(Scale factors are chosen based on a maximum absolute value of the initial higher-precision format. The power-of-two format values allow for the lower-precision data elements to be a division result of the higher-precision data elements.). As per claim 8: Khailany disclosed the processing device of claim 7, wherein the un-scaled data elements are output activations of a neural network layer (Khailany: Figure 3A element 310, paragraphs 84-89)(The output activations are un-scaled after both fine and coarse scale factors have been applied.). As per claim 10: Claim 10 essentially recites the same limitations of claim 1. Therefore, claim 10 is rejected for the same reasons as claim 1. As per claim 11: The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 2. Therefore, claim 11 is rejected for the same reason(s) as claim 2. As per claim 12: The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 3. Therefore, claim 12 is rejected for the same reason(s) as claim 3. As per claim 13: The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 4. Therefore, claim 13 is rejected for the same reason(s) as claim 4. As per claim 14: The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 5. Therefore, claim 14 is rejected for the same reason(s) as claim 5. As per claim 15: The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 6. Therefore, claim 15 is rejected for the same reason(s) as claim 6. As per claim 16: The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 7. Therefore, claim 16 is rejected for the same reason(s) as claim 7. As per claim 17: The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 8. Therefore, claim 17 is rejected for the same reason(s) as claim 8. As per claim 18: Claim 18 essentially recites the same limitations of claim 1. Therefore, claim 18 is rejected for the same reasons as claim 1. As per claim 19: The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 2. Therefore, claim 19 is rejected for the same reason(s) as claim 2. As per claim 20: The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 3. Therefore, claim 20 is rejected for the same reason(s) as claim 3 . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Khailany et al. (U.S. 2022/0067530), in view of Official Notice . As per claim 9: Khailany disclosed the processing device of claim 1, further comprising: a matrix-multiply unit (MXU) comprising a weight-stationary systolic array of processing cells, wherein a processing cell of the systolic array comprises a data register for storing the gains block and a scale factor register for storing the gains scale factor (Khailany: Figures 1B and 3B elements 130-132 and 365, paragraphs 47-48 and 94)(Official notice is given that matrix multiply-accumulators can be implemented as systolic arrays for the advantage of increased performance. Thus, it would have been obvious to one of ordinary skill in the art to implement the MMA as a systolic array. Additionally, official notice is given that data buffers can be implemented as registers for the advantage of increased data access times. Thus, it would have been obvious to one of ordinary skill in the art to implement the weight vector and scale buffers as registers.) . Conclusion The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Tyrlik et al. (U.S. 2025/0291873), taught exponent scale factor metadata. Park et al. (U.S. 2024/0412052), taught quantizing floating-point elements prior to convolutions. Schoner et al. (U.S. 2024/0069864), taught a hardware accelerator for floating-point operations. Yun et al. (U.S. 2022/0147806), taught generating scaling factors for input and weight data. Mills (U.S. 2019/0340489), taught neural networks handling different datatypes. Vantrease et al. (U.S. 2019/0294413), taught min/max quantization prior to integer convolutions. Brothers et al. (U.S. 2016/0358068), taught reducing computations in neural networks. Gong et al. (U.S. 12,423,561), taught convolutions on transformed input activations and weights . Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov . Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACOB PETRANEK/Primary Examiner, Art Unit 2183 Application/Control Number: 19/097,425 Page 2 Art Unit: 2183 Application/Control Number: 19/097,425 Page 3 Art Unit: 2183 Application/Control Number: 19/097,425 Page 4 Art Unit: 2183
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