DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure remains objected to because of the following informalities: the title of the invention is not descriptive of the invention and is not technically accurate in such a way as to clearly convey what Applicant considers to be the novelty and assist readers in deciding whether there is a need for consulting the full patent text for details.
Response to Arguments
Applicant's arguments filed 02/01/2026 have been fully considered but they are not persuasive due to the nature of how vague and overbroad the claims are. However, in the interest of moving prosecution forward, the Office has supplemented the teaching of CHO et al. of the last Official action with that of Kuronuma et al. (US 2003/020651).
Applicant’s Representative argues on page 8 of the remarks that there is no discussion on Cho with respect to “a DMA that generates a memory request based on the control message that was generated by the host core.”
The Office respectfully disagrees and would like to point out that the claimed “DMA” generates “a memory request in response to a control message” but does not generate “a memory request based on the control message that was generated by the host core.” Furthermore, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a DMA that generates a memory request based on the control message that was generated by the host core) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s Representative further argues on page 8 of the remarks that there is no discussion in Cho regarding “the host memory generating a memory request based on a control message where the control message controls the DMA and is generated by a host core.”
The Office respectfully disagrees. The claim does not recite that “the control message is generated by a host core.” Instead, the claim recites “a host core configured to generate the control message;” and as claimed we do not know whether the claimed “control message” was ever generated.
Applicant’s Representative argues on page 9 of the remarks that Cho does not generate a memory request based on a control message where the control message controls the DMA and is generated by a host core.
The Office respectfully disagrees. The claim does not recite “generating a memory request based on a control message where the control message controls the DMA and is generated by a host core.” Instead, the claim recites “a host core configured to generate the control message;” and as claimed we do not know whether the claimed “control message” was ever generated.
Regarding claim 3, applicant’s Representative argues on page 10 of the remarks that there is no discussion in Kim regarding a DMA generating the memory request via a processing in memory (PIM) host program.
The Office respectfully disagrees. Claim 3 was rejected over the combination of Cho and Kim and Cho is relied upon for teaching a DMA configured to generate memory request, which request is through a processor core and Kim discloses a processing in memory (PIM) executing memory request such as read-write operations. Additionally, as stated above, the claimed DMA does not actually generate anything but is simply configured to generate a request at some time in the future or perhaps never.
Applicant’s Representative further argues on pages 10-12 of the remarks that there is no motivation for one of ordinary skill in the art to modify Kim to change the processor core to DMA and further have the DMA to generate a memory request in response to a control message that controls the DMA and still further to modify the DMA to generate the memory request via a processing in memory (PIM host program.
In view of the Supreme Court decision in KSR International Co. v. Teleflex Inc., when a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one. If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill.
Still further, the court states that “the focus when making a determination of obviousness should be on what a person of ordinary skill in the pertinent art would have known at the time of the invention…and this is regardless of whether the source of that knowledge and ability was documentary prior art, general knowledge in the art, or just common sense”.
Finally, for purposes of 35 U.S.C 103, prior art can be either in the field of applicant’s endeavor or be reasonably pertinent to the particular problem with which the applicant was concerned. Furthermore, prior art that is in a field of endeavor other than that of the applicant, or solves a problem which is different from that which the applicant was trying to solve, may also be considered for the purposes of 35 U.S.C 103. See, e.g., In re KSR International Co. v. Teleflex Inc., 550 U.S. at_,82 USPQ2d at 1396 (2007).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13, 15, and 20-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,287,987. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the issued patent make obvious the claims of the pending application in that the limitations claimed in the pending application are similarly claimed in the issued patents and the claims are directed to substantially the same subject matter as the parent case though not necessarily presented in the same sequential order or the same claim numbering as shown in the table below (for purposes of illustration).
Instant Application: 19/097,438
Patent: 12,287,987
Claim 1. A data processing apparatus comprising: a direct memory access (DMA) that generates a memory request in response to a control message that controls the DMA; a host core configured to generate the control message; a memory controller configured to generate a memory command based on the memory request generated by the DMA; and a processor configured to perform an operation in a memory based on the memory command.
Claim 3. The data processing apparatus of claim 1, wherein the DMA is further configured to generate the memory request via a processing in memory (PIM) host program.
Claim 1. A data processing apparatus comprising: a host core configured to generate a control message to control a direct memory access (DMA); the DMA configured to generate a memory request based on the control message; a memory controller configured to generate a memory command based on the memory request; and a processor configured to perform an operation in a memory based on the memory command, wherein the DMA comprises a processinq in memory (PIM) host program.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 7-8, 10, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO et al. (US 20200151109 A1) and Kuronuma et al. (US 2003/0204651).
Regarding claim 1, CHO et al. discloses a data processing apparatus comprising: a direct memory access (DMA) that generates a memory request in response to a control message [FIG. 3, 4; ¶0035: storage device access host memory and control operations of the host through a DMA operation]; a host core configured to generate the control message [¶0041: the controller communicates with the host memory for accessing the host memory depending on a request of the processor core]; a memory controller configured to generate a memory command based on the memory request generated by the DMA [¶0041: the controller communicates with the host memory for accessing the host memory depending on a request of the processor core]; and a processor configured to perform an operation in a memory based on the memory command [¶0041: the controller communicates with the host memory for accessing the host memory depending on a request of the processor core].
Cho does not explicitly disclose a control message that controls the DMA.
Kuronuma et al., however, discloses generate a memory request in response to a control message that controls the DMA [Abstract, ¶0048].
It would have been obvious to one of ordinary skill in the art to have a control message that controls the DMA in order to provide a memory control system for access a memory (¶0047).
Regarding claim 7, CHO et al. discloses the data processing apparatus of claim 1, wherein the operation is performed usinq a memory, and the memory comprises a dynamic random access memory (DRAM) [¶0004].
Regarding claims 8 and 23, CHO et al. discloses the data processing apparatus of claim 7, wherein the DRAM comprises one or any combination of a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power DDR (LPDDR), and a high bandwidth memory (HBM) [¶0022].
Regarding claim 10, the rationale in the rejection of claim 1 is herein incorporated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO et al. (US 20200151109 A1), Kuronuma et al. (US 2003/0204651) AND CN112748859 (See Corresponding Machine Translation).
Regarding claim 2, CHO et al. discloses the data processing apparatus of claim 1, but does not explicitly disclose wherein the host core comprises a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), an advanced reduced instruction set computer (RISC) machine (ARM), or a field programmable gate array (FPGA).
CN112748859, however, discloses wherein the host core comprises a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), an advanced reduced instruction set computer (RISC) machine (ARM), or a field programmable gate array (FPGA) [English Translation; Description Section; Full Paragraph 36: the main board of the host chip is provided with a CPU].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have the host core comprises a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), an advanced reduced instruction set computer (RISC) machine (ARM), or a field programmable gate array (FPGA) in order to improve the read/write speed of the data (Abstract).
Regarding claim 11, the rationale in the rejection of claim 2 is herein incorporated.
Claim(s) 3, 4-6, 9, 10, 12-13, 15, 20, 22, 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO et al. (US 20200151109 A1), Kuronuma et al. (US 2003/0204651) and KIM (WO 2022010016).
Regarding claim 3, CHO et al. discloses the data processing apparatus of claim 1, but does not explicitly disclose wherein the DMA is further configured to generate the memory request via a processing in memory (PIM) host program.
KIM, however, discloses wherein the DMA is further configured to generate the memory request via a processing in memory (PIM) host program [Abstract: a processing-in-memory device and a method for including a read-write-operation instruction and processing the read-write-operation instruction to maximize performance of PIM].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention to have the DMA being further configured to generate the memory request via a processing in memory (PIM) host program in order to process the read-write-operation instruction and maximize the performance of the PIM (Abstract].
Regarding claim 4, KIM et al. discloses the data processing apparatus of claim 3, wherein the DMA is further configured to generate a read request or a write request via the PIM host program [Abstract: a processing-in-memory device and a method for including a read-write-operation instruction and processing the read-write-operation instruction to maximize performance of PIM].
Regarding claim 5, KIM et al. discloses the data processing apparatus of claim 3, wherein the DMA is further configured to generate the memory request in an in-order form via the PIM host program [Abstract].
Regarding claim 6, KIM et al. discloses the data processing apparatus of claim 1, wherein the memory controller is further configured to convert the memory request into the memory command comprising any one or any combination of an active command, a precharge command, a refresh command, a read command, and a write command [Abstract].
Regarding claim 9, KIM et al. discloses the data processing apparatus of claim 1, wherein the processor is further configured to perform the operation via a PIM device program [Abstract].
Regarding claim 10, the rationale in the rejection of claim 1 is herein incorporated. Cho further discloses a host core generating a control message to control a direct memory access (DMA) [¶0032, 0035: storage device access host memory and control operations of the host through a DMA operation wherein a controller is included in the host]; generating by the DMA a memory request based on the control message [¶0035: storage device access host memory and control operations of the host through a DMA operation]; generating by a memory controller a memory command based on the memory request [¶0041: the controller communicates with the host memory for accessing the host memory depending on a request of the processor core].
KIM further discloses performing by a processor in memory (PIM) an operation based on the memory command [Abstract: a processing-in-memory device and a method for including a read-write-operation instruction and processing the read-write-operation instruction to maximize performance of PIM].
Regarding claim 12, the rationale in the rejection of claim 3 is herein incorporated.
Regarding claim 13, the rationale in the rejection of claim 4 is herein incorporated.
Regarding claim 14, the rationale in the rejection of claim 5 is herein incorporated.
14. (Canceled).
Regarding claim 15, the rationale in the rejection of claim 6 is herein incorporated.
16-19. (Canceled).
Regarding claim 20, CHO et al. discloses the system of claim 20, wherein the control message is a message for controlling a data transaction operation between the host core and a memory, or at the memory [¶0032, 0035: storage device access host memory and control operations of the host through a DMA operation wherein a controller is included in the host.
Regarding claim 22, KIM et al. discloses the system of claim 21, further comprising the memory controller, wherein the memory command corresponds to a conversion result, by the memory controller, of the memory request, and wherein the memory command comprises at least one of an active command, a precharge command, a refresh command, a read command, or a write command [Abstract].
Regarding claim 24, KIM et al. discloses the system of claim 20, wherein the generation of the memory request comprises a generation of the memory request, as a read request or a write request, using a processing in memory (PIM) host program [Abstract: a processing-in-memory device and a method for including a read-write-operation instruction and processing the read-write-operation instruction to maximize performance of PIM].
Regarding claim 25, KIM et al. discloses the system of claim 20, wherein the generation of the memory request comprises a generation of the memory request in an in-order form using a processing in memory (PIM) host program [Abstract].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. KUYEL (2021/0255956) discloses a microprocessor-based system memory manager hardware accelerator wherein a memory device may perform one or more erase, program, and read operations under the control of the memory controller.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARDOCHEE CHERY whose telephone number is (571)272-4246. The examiner can normally be reached from 900-500.
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Respectfully Submitted,
USPTO
Dated: March 23, 2026 By: /MARDOCHEE CHERY/
Primary Examiner
Art Unit 2133
Email:Mardochee.Chery@uspto.gov Telephone: 571-272-4246
Facsimile: 571-273-4246