DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 9-10, 12-14 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jean et al. (US2021/0334016).
With respect claim 1, Jean et al. teaches one or more memory devices (see Fig. 2 and paragraph 25; NVM device 212 in memory device 210); and
processing circuitry coupled with the one or more memory devices (see Fig. 2 and paragraph 24; host device 205 coupled to memory device) and configured to cause the memory system to:
receive a first security protocol command that indicates data associated with an access operation for a memory array of the memory system (see paragraph 25 and 55; RPMB command can be received, such as at a memory device from a host device. The RPMB command can include an RPMB write command, an RPMB read command);
initiate, at a first time based at least in part on the first security protocol command, the access operation associated with accessing the data at the memory array of the memory system (see paragraph 56-57; queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order… the RPMB operations can be performed in order (i.e., RPMB write command begins to execute); and
receive, after the first time, concurrent with performing the access operation, and before a second time at which the access operation is complete, a second security protocol command that requests transmission of the data to a host device (see paragraphs 46, 56-57 and 83; queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order… the RPMB operations can be performed in order. However, certain parallel operations may be performed to speed the RPMB process. In an example, at 705, RPMB read data can be pre-fetched out of order and stored in volatile memory of the memory device at 706. When the RPMB read operation is ready to be performed at 704, the information can be retrieved from volatile memory (i.e., while a RPMB write command in performed, a read command may be received and data is prefetched)).
With respect claim 3, Jean et al. teaches wherein, to initiate the access operation, the processing circuitry is configured to cause the memory system to: initiate a read operation based at least in part on the first security protocol command indicating the data to be read from the memory system (see paragraphs 55 and 83; RPMB command can be received, such as at a memory device from a host device. The RPMB command can include an RPMB read command… perform RPMB commands in order according to the RPMB command queue, wherein the memory device is configured to pre-fetch read data from a read address associated with a queued RPMB read command out of order and store the pre-fetched read data in volatile memory of the memory device to be provided to the host device).
With respect claim 4, Jean et al. teaches wherein the processing circuitry is further configured to cause the memory system to: transmit, to the host device after the second time at which the read operation is complete, the data based at least in part on the second security protocol command (see paragraphs 46 and 57; the memory device can read data from read addresses associated with queued read commands (e.g., out of order) and store the data in volatile memory (e.g., SDRAM, etc.) on the memory device until the corresponding RPMB command is executed in order, thereby having the data immediately for transfer to the host device or one or more other device coupled to the memory device).
With respect claim 5, Jean et al. teaches wherein, to initiate the access operation, the processing circuitry is configured to cause the memory system to: initiate a write operation based at least in part on the first security protocol command indicating the data to be written to the memory system (see paragraphs 55 and 83; RPMB command can be received, such as at a memory device from a host device. The RPMB command can include an RPMB write command).
With respect claim 9, Jean et al. teaches wherein the first security protocol command and the second security protocol command are associated with access to a replay protected memory block (see paragraphs 16 and 83; receive Replay Protected Memory Block (RPMB) commands from a host device).
With respect claim 10, Jean et al. teaches a non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system (see paragraph 71-72; computer-readable medium), cause the memory system to:
receive a first security protocol command that indicates data associated with an access operation for a memory array of the memory system (see paragraph 25 and 55; RPMB command can be received, such as at a memory device from a host device. The RPMB command can include an RPMB write command, an RPMB read command);
initiate, at a first time based at least in part on the first security protocol command, the access operation associated with accessing the data at the memory array of the memory system (see paragraph 56-57; queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order… the RPMB operations can be performed in order (i.e., RPMB write command begins to execute); and
receive, after the first time, concurrent with performing the access operation, and before a second time at which the access operation is complete, a second security protocol command that requests transmission of the data to a host device (see paragraphs 46, 56-57 and 83; queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order… the RPMB operations can be performed in order. However, certain parallel operations may be performed to speed the RPMB process. In an example, at 705, RPMB read data can be pre-fetched out of order and stored in volatile memory of the memory device at 706. When the RPMB read operation is ready to be performed at 704, the information can be retrieved from volatile memory (i.e., while a RPMB write command in performed, a read command may be received and data is prefetched)).
With respect claim 12, Jean et al. teaches wherein the instructions to initiate the access operation, when executed by the one or more processors of the memory system, cause the memory system to: initiate a read operation based at least in part on the first security protocol command indicating the data to be read from the memory system (see paragraphs 55 and 83; RPMB command can be received, such as at a memory device from a host device. The RPMB command can include an RPMB read command… perform RPMB commands in order according to the RPMB command queue, wherein the memory device is configured to pre-fetch read data from a read address associated with a queued RPMB read command out of order and store the pre-fetched read data in volatile memory of the memory device to be provided to the host device).
With respect claim 13, Jean et al. teaches wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: transmit, to the host device after the second time at which the read operation is complete, the data based at least in part on the second security protocol command (see paragraphs 46 and 57; the memory device can read data from read addresses associated with queued read commands (e.g., out of order) and store the data in volatile memory (e.g., SDRAM, etc.) on the memory device until the corresponding RPMB command is executed in order, thereby having the data immediately for transfer to the host device or one or more other device coupled to the memory device).
With respect claim 14, Jean et al. teaches wherein the instructions to initiate the access operation, when executed by the one or more processors of the memory system, cause the memory system to: initiate a write operation based at least in part on the first security protocol command indicating the data to be written to the memory system (see paragraphs 55 and 83; RPMB command can be received, such as at a memory device from a host device. The RPMB command can include an RPMB write command).
With respect claim 18, Jean et al. teaches wherein the first security protocol command and the second security protocol command are associated with access to a replay protected memory block (see paragraphs 16 and 83; receive Replay Protected Memory Block (RPMB) commands from a host device).
With respect claim 19, Jean t al. teaches receiving a first security protocol command that indicates data associated with an access operation for a memory array of the memory system (see paragraph 25 and 55; RPMB command can be received, such as at a memory device from a host device. The RPMB command can include an RPMB write command, an RPMB read command);
initiating, at a first time based at least in part on the first security protocol command, the access operation associated with accessing the data at the memory array of the memory system (see paragraph 56-57; queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order… the RPMB operations can be performed in order (i.e., RPMB write command begins to execute); and
receiving, after the first time, concurrent with performing the access operation, and before a second time at which the access operation is complete, a second security protocol command that requests transmission of the data to a host device (see paragraph 46, 56-57 and 83; queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order… the RPMB operations can be performed in order. However, certain parallel operations may be performed to speed the RPMB process. In an example, at 705, RPMB read data can be pre-fetched out of order and stored in volatile memory of the memory device at 706. When the RPMB read operation is ready to be performed at 704, the information can be retrieved from volatile memory (i.e., while a RPMB write command in performed, a read command may be received and data is prefetched)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 6-8, 11, 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jean et al. (US2021/0334016) in view of Lee (US2021/0334016).
With respect claim 2, Jean et al. teaches wherein the processing circuitry is further configured to cause the memory system to: verify the first security protocol command (see paragraph 25; check such request for access to a protected partition of the NVM device 212, such as an RPMB partition 221 separate from a user partition or other portion of the NVM 213. If a valid command is confirmed, the memory device RPMB circuit 218 can enable communication of RPMB data between the host device 205 and the RPMB partition 221).
Jean et al. does not teach transmit, before the first time or concurrent with performing the access operation, a response to the first security protocol command based at least in part on verifying the first security protocol command, the response indicating a status of the memory system based at least in part on the first security protocol command, wherein the second security protocol command is received based at least in part on the response.
However, Lee teaches wherein the host 300 may provide a command protocol unit (Command PIU) to the storage device 50. The Command PIU provided in step S1301 may include an RPMB message. The storage device 50 may perform an authentication operation for the RPMB using the message authentication code (MAC) and metadata included in the RPMB message. In step S1303, the storage device 50 may provide a ready to transfer protocol unit (Ready To Transfer PIU) to the host 300. The Ready To Transfer PIU may be a protocol unit provided when the storage device 50 is ready to receive data to be provided by the host 300. In an embodiment, the Ready To Transfer PIU may be a protocol unit that provides a message indicating that it is ready to receive a data out protocol unit (Data Out PIU). In step S1305, the host 300 may provide the Data Out PIU to the storage device 50. In step S1307, the storage device 50 may provide a response protocol unit (Response PIU) to the host 300. (see paragraphs 222-224).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 6, Jean et al. teaches wherein the processing circuitry is further configured to cause the memory system to: receive, concurrent with performing the write operation, a third security protocol command that requests a read of the data indicated via the first security protocol command (see paragraph 56; commands can be queued in the order they are received. In certain examples, the write commands can be queued in the order they are received, and the read commands can be performed out of order.... An example queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order).
Jean et al. does not teach transmit, to the host device after the second time at which the write operation is complete, second data that indicates a result of the write operation based at least in part on the read of the data and the second security protocol command that requests the transmission of the data to the host device.
However, Lee teaches wherein the storage device 50 may provide the host 300 with a third response including the result of the program operation on the write data, in response to the third request. The result of the program operation may include information indicating whether the program operation has passed or failed. The result of the program operation may include information indicating whether the write data has integrity (see paragraph 149).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 7, Jean et al. does not teach wherein the processing circuitry is further configured to cause the memory system to: transmit, to the host device based at least in part on the first security protocol command, at least one first information unit that indicates that the memory system is ready to receive the data; and receive, based at least in part on the transmission of the at least one first information unit, at least one second information unit comprising at least a portion of the data, wherein the access operation comprises a write operation to write the data based at least in part on the at least one second information unit.
However, Lee teaches wherein host 300 may provide a command protocol unit (Command PIU) to the storage device 50. The Command PIU provided in step S1501 may include an RPMB message. The storage device 50 may perform an authentication operation for the RPMB using the message authentication code (MAC) and metadata included in the RPMB message [0244] In step S1503, the storage device 50 may provide a transfer preparation protocol unit (Ready To Transfer PIU) to the host 300. The Ready To Transfer PIU may be a protocol unit provided when the storage device 50 is ready to receive data from the host 300. In an embodiment, the Ready To Transfer PIU may be a protocol unit that provides a message indicating that the storage device 50 is ready to receive a data out protocol unit (Data Out PIU) from the host 300. In step S1505, the host 300 may provide the Data Out PIU to the storage device 50. The Data Out PIU may include a plurality of data segments including data to be stored in the RPMB. In step S1507, the storage device 50 may provide a response protocol unit (Response PIU) to the host 300. The Response PIU may include a result of performing an RPMB write operation (see paragraphs 243-246).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 8, Jean et al. does not teach wherein the processing circuitry is further configured to cause the memory system to: transmit, to the host device based at least in part on the first security protocol command, at least one first information unit that indicates that the memory system is ready to receive an indication of the data; and receive, based at least in part on the transmission of the at least one first information unit, at least one second information unit comprising the indication of the data, wherein the access operation comprises a read operation to read the indicated data based at least in part on the at least one second information unit.
However, Lee teaches wherein the host 300 may provide a command protocol unit (Command PIU) to the storage device 50. The Command PIU provided in step S1301 may include an RPMB message. The storage device 50 may perform an authentication operation for the RPMB using the message authentication code (MAC) and metadata included in the RPMB message. In step S1303, the storage device 50 may provide a ready to transfer protocol unit (Ready To Transfer PIU) to the host 300. The Ready To Transfer PIU may be a protocol unit provided when the storage device 50 is ready to receive data to be provided by the host 300. In an embodiment, the Ready To Transfer PIU may be a protocol unit that provides a message indicating that it is ready to receive a data out protocol unit (Data Out PIU). In step S1305, the host 300 may provide the Data Out PIU to the storage device 50. In step S1307, the storage device 50 may provide a response protocol unit (Response PIU) to the host 300. The Response PIU provided by the storage device 50 may include a result of normally receiving a request for performing an RPMB read operation (see paragraphs 222-225).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 11, Jean et al. teaches wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: verify the first security protocol command (see paragraph 25; check such request for access to a protected partition of the NVM device 212, such as an RPMB partition 221 separate from a user partition or other portion of the NVM 213. If a valid command is confirmed, the memory device RPMB circuit 218 can enable communication of RPMB data between the host device 205 and the RPMB partition 221).
Jean et al. does not teach transmit, before the first time or concurrent with performing the access operation, a response to the first security protocol command based at least in part on verifying the first security protocol command, the response indicating a status of the memory system based at least in part on the first security protocol command, wherein the second security protocol command is received based at least in part on the response.
However, Lee teaches wherein the host 300 may provide a command protocol unit (Command PIU) to the storage device 50. The Command PIU provided in step S1301 may include an RPMB message. The storage device 50 may perform an authentication operation for the RPMB using the message authentication code (MAC) and metadata included in the RPMB message. In step S1303, the storage device 50 may provide a ready to transfer protocol unit (Ready To Transfer PIU) to the host 300. The Ready To Transfer PIU may be a protocol unit provided when the storage device 50 is ready to receive data to be provided by the host 300. In an embodiment, the Ready To Transfer PIU may be a protocol unit that provides a message indicating that it is ready to receive a data out protocol unit (Data Out PIU). In step S1305, the host 300 may provide the Data Out PIU to the storage device 50. In step S1307, the storage device 50 may provide a response protocol unit (Response PIU) to the host 300. (see paragraphs 222-224).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 15, Jean et al. teaches wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: receive, concurrent with performing the write operation, a third security protocol command that requests a read of the data indicated via the first security protocol command (see paragraph 56; commands can be queued in the order they are received. In certain examples, the write commands can be queued in the order they are received, and the read commands can be performed out of order.... An example queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order).
Jean et al. does not teach transmit, to the host device after the second time at which the write operation is complete, second data that indicates a result of the write operation based at least in part on the read of the data and the second security protocol command that requests the transmission of the data to the host device.
However, Lee teaches wherein the storage device 50 may provide the host 300 with a third response including the result of the program operation on the write data, in response to the third request. The result of the program operation may include information indicating whether the program operation has passed or failed. The result of the program operation may include information indicating whether the write data has integrity (see paragraph 149).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 16, Jean et al. does not teach wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: transmit, to the host device based at least in part on the first security protocol command, at least one first information unit that indicates that the memory system is ready to receive the data; and receive, based at least in part on the transmission of the at least one first information unit, at least one second information unit comprising at least a portion of the data, wherein the access operation comprises a write operation to write the data based at least in part on the at least one second information unit.
However, Lee teaches wherein host 300 may provide a command protocol unit (Command PIU) to the storage device 50. The Command PIU provided in step S1501 may include an RPMB message. The storage device 50 may perform an authentication operation for the RPMB using the message authentication code (MAC) and metadata included in the RPMB message [0244] In step S1503, the storage device 50 may provide a transfer preparation protocol unit (Ready To Transfer PIU) to the host 300. The Ready To Transfer PIU may be a protocol unit provided when the storage device 50 is ready to receive data from the host 300. In an embodiment, the Ready To Transfer PIU may be a protocol unit that provides a message indicating that the storage device 50 is ready to receive a data out protocol unit (Data Out PIU) from the host 300. In step S1505, the host 300 may provide the Data Out PIU to the storage device 50. The Data Out PIU may include a plurality of data segments including data to be stored in the RPMB. In step S1507, the storage device 50 may provide a response protocol unit (Response PIU) to the host 300. The Response PIU may include a result of performing an RPMB write operation (see paragraphs 243-246).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 17, Jean et al. does not teach wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: transmit, to the host device based at least in part on the first security protocol command, at least one first information unit that indicates that the memory system is ready to receive an indication of the data; and receive, based at least in part on the transmission of the at least one first information unit, at least one second information unit comprising the indication of the data, wherein the access operation comprises a read operation to read the indicated data based at least in part on the at least one second information unit.
However, Lee teaches wherein the host 300 may provide a command protocol unit (Command PIU) to the storage device 50. The Command PIU provided in step S1301 may include an RPMB message. The storage device 50 may perform an authentication operation for the RPMB using the message authentication code (MAC) and metadata included in the RPMB message. In step S1303, the storage device 50 may provide a ready to transfer protocol unit (Ready To Transfer PIU) to the host 300. The Ready To Transfer PIU may be a protocol unit provided when the storage device 50 is ready to receive data to be provided by the host 300. In an embodiment, the Ready To Transfer PIU may be a protocol unit that provides a message indicating that it is ready to receive a data out protocol unit (Data Out PIU). In step S1305, the host 300 may provide the Data Out PIU to the storage device 50. In step S1307, the storage device 50 may provide a response protocol unit (Response PIU) to the host 300. The Response PIU provided by the storage device 50 may include a result of normally receiving a request for performing an RPMB read operation (see paragraphs 222-225).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
With respect claim 20, Jean et al. teaches verifying the first security protocol command (see paragraph 25; check such request for access to a protected partition of the NVM device 212, such as an RPMB partition 221 separate from a user partition or other portion of the NVM 213. If a valid command is confirmed, the memory device RPMB circuit 218 can enable communication of RPMB data between the host device 205 and the RPMB partition 221); and
Jean et al. does not teach transmitting, before the first time or concurrent with performing the access operation, a response to the first security protocol command based at least in part on verifying the first security protocol command, the response indicating a status of the memory system based at least in part on the first security protocol command, wherein the second security protocol command is received based at least in part on the response.
However, Lee teaches wherein the host 300 may provide a command protocol unit (Command PIU) to the storage device 50. The Command PIU provided in step S1301 may include an RPMB message. The storage device 50 may perform an authentication operation for the RPMB using the message authentication code (MAC) and metadata included in the RPMB message. In step S1303, the storage device 50 may provide a ready to transfer protocol unit (Ready To Transfer PIU) to the host 300. The Ready To Transfer PIU may be a protocol unit provided when the storage device 50 is ready to receive data to be provided by the host 300. In an embodiment, the Ready To Transfer PIU may be a protocol unit that provides a message indicating that it is ready to receive a data out protocol unit (Data Out PIU). In step S1305, the host 300 may provide the Data Out PIU to the storage device 50. In step S1307, the storage device 50 may provide a response protocol unit (Response PIU) to the host 300. (see paragraphs 222-224).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jean et al. to include the above mentioned to improve security read performance (see Lee, paragraph 6, 48 and 339).
Response to Arguments
Applicant's arguments filed 07/09/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues, in pages 8-10, that Jean et al. (US2021/0334016) does not teach “receive, after the first time, concurrent with performing the access operation, and before a second time at which the access operation is complete, a second security protocol command that requests transmission of the data to a host device” as recited in claims 1 and 10. Applicant’s representative argues that it is not explained how Jean et al. teaches “receiving a second security protocol command concurrently with performing the access operation”.
In response: the Examiner disagrees. Jean et al. teaches wherein queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command, having a specific order… the RPMB operations can be performed in order. However, certain parallel operations may be performed to speed the RPMB process. In an example, at 705, RPMB read data can be pre-fetched out of order and stored in volatile memory of the memory device at 706. When the RPMB read operation is ready to be performed at 704, the information can be retrieved from volatile memory (i.e., while a RPMB write command in performed, a read command may be received and data is prefetched) (see paragraphs 46, 56-57 and 83). Jean et al. teaches initiating prefetch operations in response to read commands stored in the queue; and when the read command is obtained/received for execution, the data prefetched in volatile memory is transmitted to the host while the device keeps prefetching data for the read commands in the queue.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US2022/0091757) teaches and apparatus may include a data storage device including a replay protected memory block accessed by a security protocol and a processor configured to generate a command information unit instructing the data storage device to access the replay protected memory block.
Samsonov et al. (US2016/0379015) teaches implementing replay protected storage.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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