DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the recitation of “a first circuit configured ..to deactivate the first control signal responsive to a third control signal” (lines 2-3) in which a third control signal is understood to be the signal “OSCSTOP”; and a further recitation of “wherein the third circuit is configured to activate the third control signal when a count value reach a first value” (lines 7-8) refers to the signal OSCEN (see paragraph 0020). It is unclear whether the third control signal is the signal OSCSTOP or the signal OSCEN, thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
In claim 5, the recitation of “a fourth circuit coupled to the third circuit and configured to generate an oscillation signal until the count value reaches the second value” is indefinite because it is incorrect. Paragraph 0020 states the OSCEN activates the oscillator (260, i.e. a fourth circuit) to generate an oscillation signal (OSC) when the count values exceeds an initial value. The OSCSTOP is generated when the count value is at a second value K. Thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
Claims 2-4, 6-9 are indefinite because of the technical deficiencies of claim 1.
Allowable Subject Matter
Claims 10-20 are presently allowed.
Claims 1-9 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, Lan (USP 12,627,282), discloses a control device coupled to an oscillator circuit and includes a first output circuit, a synchronizer circuit, a hysteresis circuit, a stable circuit, and a second output circuit is provided. The first output circuit activates an oscillator circuit according to an activation signal so that the oscillator circuit generates an input clock. The synchronizer circuit synchronizes the activation signal to generate a synchronization signal. The synchronization signal is synchronized with the input clock. The hysteresis circuit directs the first output circuit to disable the oscillator circuit according to the synchronization signal. The stable circuit enables a transmission signal according to the input clock. When the transmission signal is enabled, the second output circuit uses the input clock as an output clock. However, Lan reference fails to teach or fairly suggest a first circuit configured to activate a first control signal responsive to a second control signal and deactivate the first control signal responsive to a third control signal; and a third circuit coupled to the second circuit and configured to count the clock signal, wherein the third circuit is configured to activate the third control signal when a count value reaches a first value and activate a fourth control signal when a count value reaches a second value greater than the first value, and wherein a difference between the second value and the first value is the predetermined clock as called for in claim 1; a first counter circuit configured to count the clock signal, deactivate a third signal when a count value reaches M, and activate the second signal when the count value reaches K, wherein K is less than M and equal to or more than M-N as called for in claim 10; an enable control circuit configured to activate a first enable signal responsive to a start signal and deactivate the first enable signal responsive to an end signal; and a counter circuit configured to count the second clock signal, generate a third enable signal when a count value reaches a first value, and generate the end signal before the count value reaches the first value as called for in claim 17.
Conclusion
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/TUAN T LAM/ Primary Examiner, Art Unit 2836
9/29/2026
