Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 01 April 2025 for application number 19/097,739. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 16 August 2024 (KR10-2024-0109710).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01 April 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Specification
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner believes that the title of the invention is imprecise. A descriptive title indicative of the invention will help in proper indexing, classifying, searching, etc. See MPEP 606.01. However, the title of the invention should be limited to 500 characters.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites in the second limitation “an indexer configured to, based on a stripe request from the processing circuit, assign respectively different indices from 1 to n to sub-blocks included in each of a plurality of memory blocks of the non-volatile memory…” It is unclear if the respectfully different indices from 1 to n are talking about the blocks or the sub-blocks. It is unclear if the indices from 1 to n are 1 to n sub-blocks that are part of one memory block, of if it is with respect to 1 to n memory blocks that have the indices. It is unclear if each memory block has sub-blocks 1 to n, or if each of the sub-blocks as assigned 1 to n. So it is unclear what the “respectfully different” is comparing. Examiner suggests to provide clarifying language to clearly claim which types of blocks have the indices 1 to n, to overcome the rejection. Claims 8 and 14 recite similar language and are rejected with like reasoning. Claims 2 – 7, 9 – 13, and 15 – 20 depend from claims 1, 8, and 14 and are rejected base upon their dependency.
Claim 1 recites in the last limitation “each of the plurality of memory blocks to assemble first selected sub-blocks having at least indices from 1 to n.” It is unclear if each plurality includes index 1 and index n, or if each of the indices have to be between 1 and n. Based on the claim language, it appears a superblock has to include at least two indices from 1 and n, but could also include indices greater than n with respect to the “at least indices from 1 to n.” Examiner suggests to provide clarifying language to clearly claim with respect to indexing the memory blocks / sub-blocks for each superblock, to overcome the rejection. Claims 8 and 14 recite similar language and are rejected with like reasoning. Claims 2 – 7, 9 – 13, and 15 – 20 depend from claims 1, 8, and 14 and are rejected base upon their dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 8, 9, 13, 14, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Muchheria et al. [hereafter as Muchheria], US Pub. No. 2021/0034274 A1 in view of Cheng [hereafter as Cheng], US Pub. No. 2024/0361934 A1.
As per claim 1, Muchheria discloses a memory controller comprising:
a processing circuit configured to, based on a first write command from a host [“The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110.”] [para. 0022], control a non-volatile memory to write data to sub-blocks [blocks] included in a first super-block in a parallel manner to each other [“Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel.”] [para. 0029] [“As new blocks are written on memory components 112A to 112N controller 115 can add a corresponding entry to the index and assign an index number. The index number can have a value that is increment by one unit each time a new index number is assigned. Thus, the value of the index number is indicative of the age of data stored on a block, as more recently written blocks can be assigned a higher index number than previously written blocks. When a block is erased and/or overwritten with new data, controller 115 can assign a new index number to the blocks.”] [para. 0030] [para. 0032];
an indexer [controller] configured to, based on a stripe request from the processing circuit, assign respectively different indices from 1 to n to sub-blocks included in each of a plurality of memory blocks of the non-volatile memory based on a characteristic parameter [age], wherein n is a natural number greater than or equal to 2 [“In one embodiment, controller 115 maintains an index of all blocks stored on memory components 112A to 112N. For example, the index can include a list of the blocks and a sequential index number assigned to each of blocks. As new blocks are written on memory components 112A to 112N controller 115 can add a corresponding entry to the index and assign an index number. The index number can have a value that is increment by one unit each time a new index number is assigned. Thus, the value of the index number is indicative of the age of data stored on a block, as more recently written blocks can be assigned a higher index number than previously written blocks. When a block is erased and/or overwritten with new data, controller 115 can assign a new index number to the blocks. In one embodiment, controller 115 maintains the index in local memory 119.”] [para. 0030].
However, Muchheria does not explicitly disclose a super-block constructor configured to:
select one sub-block of the sub-blocks in each of the plurality of memory blocks to obtain selected sub-blocks, and
assemble the selected sub-blocks to construct the first super-block,
wherein the super-block constructor is configured to select one sub-block of the sub-blocks in each of the plurality of memory blocks to assemble first selected sub-blocks having at least indices from 1 to n.
Cheng teaches a super-block constructor [“the memory controller …” [Abstract] configured to:
select one sub-block of the sub-blocks in each of the plurality of memory blocks to obtain selected sub-blocks [“the memory controller selects one from multiple superblocks as a first target superblock of the write operation and sequentially writes the portions of the predetermined data into the pages of the first target superblock in a cyclic manner among memory dies according to an order of plane indices.” [Abstract], and
assemble the selected sub-blocks to construct the first super-block [“Taking the write order shown in FIG. 4 as an example, in the write operation of the predetermined data, corresponding write operations performed on the pages of a target superblock comprise, in a chronological order, the corresponding write operation performed on the first page on the first plane (e.g., the plane Plane[0]) of the first memory die (e.g., the memory die Die[0]), the corresponding write operation performed on the first page on the first plane of the second memory die (e.g., the memory die Die[1]), …”] [para. 0056],
wherein the super-block constructor is configured to select one sub-block of the sub-blocks in each of the plurality of memory blocks [the memory controller selects one from the superblocks as a first target superblock of the write operation and sequentially writes a plurality of portions of the predetermined data into the pages of the first target superblock in a cyclic manner among the memory dies according to an order of the plane indices] to assemble first selected sub-blocks having at least indices from 1 to n [“the memory controller performs a write operation to write predetermined data into the memory device, and in the write operation, the memory controller selects one from the superblocks as a first target superblock of the write operation and sequentially writes a plurality of portions of the predetermined data into the pages of the first target superblock in a cyclic manner among the memory dies according to an order of the plane indices. Each memory die comprises at least a first plane and a second plane, in the write operation of the predetermined data, and corresponding write operations performed on a first page on the first plane of all memory dies of the first target superblock are earlier than corresponding write operations performed on a first page on the second plane of all memory dies of the first target superblock.”] [para. 0003].
Muchheria and Cheng are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Muchheria with Cheng in order to modify Muchheria for “a super-block constructor configured to:
select one sub-block of the sub-blocks in each of the plurality of memory blocks to obtain selected sub-blocks, and
assemble the selected sub-blocks to construct the first super-block,
wherein the super-block constructor is configured to select one sub-block of the sub-blocks in each of the plurality of memory blocks to assemble first selected sub-blocks having at least indices from 1 to n” as taught by Cheng. One of ordinary skill in the art would be motivated to combine Muchheria with Cheng before the effective filing date of the claimed invention “to further improve the access efficiency, in some embodiments of the invention, the memory device 120 may have a multi-channel configuration, where each channel may correspond to one data bus. With multi-channel configuration, greater parallel processing benefits can be obtained when writing and reading data.” [Cheng, para. 0032].
Claim 8 is rejected with like reasoning as claim 1 above.
Claim 14 is rejected with like reasoning as claim 1 above, except for the following remaining claim limitations:
a non-volatile memory including a plurality of memory blocks respectively included in different memory dies.
Cheng teaches a non-volatile memory including a plurality of memory blocks respectively included in different memory dies [“According to an embodiment of the invention, a data storage device comprises a memory device and a memory controller. The memory device comprises a plurality of memory dies. Each memory die comprises a plurality of planes, one of the planes of each memory die corresponds to one of a plurality of plane indices, and each plane comprises a plurality of memory blocks.”].
As per claim 2, Muchheria in view of Cheng discloses the memory controller of claim 1, Cheng teaches wherein the indexer is configured to respectively assign the different indices from 1 to n to an n-number of the sub-blocks included in each of the plurality of memory blocks, based on position information of each of the sub-blocks [“Note that the ordinal numbers used here to describe the first page, the second page, the third page and the fourth page, etc. may correspond to the numbers assigned based on physical positions or physical addresses of the pages in a memory block.”] [para. 0060].
Claims 9 and 15 are rejected with like reasoning.
As per claim 6, Muchheria in view of Cheng discloses the memory controller of claim 1,
Muchheria discloses wherein the processing circuit is configured to, based on a second write command from the host, control the non-volatile memory to write data to sub-blocks included in a second super-block in a parallel manner with each other [“The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110.”] [para. 0022] [“Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel.”] [para. 0029] [“As new blocks are written on memory components 112A to 112N controller 115 can add a corresponding entry to the index and assign an index number. The index number can have a value that is increment by one unit each time a new index number is assigned. Thus, the value of the index number is indicative of the age of data stored on a block, as more recently written blocks can be assigned a higher index number than previously written blocks. When a block is erased and/or overwritten with new data, controller 115 can assign a new index number to the blocks.”] [para. 0030] [para. 0032], and
Cheng teaches wherein the super-block constructor is configured to select one sub-block not included in the first super-block from each of the plurality of memory blocks and to assemble second selected sub-blocks to construct the second super-block having at least indices from 1 to n [“The memory blocks form a plurality of superblocks. Each superblock comprises a predetermine number of the memory blocks and the predetermine number of the memory blocks are respectively in different planes of different memory dies. The memory controller is coupled to the memory device to access the memory device. In response to a write command received from a host device, the memory controller performs a write operation to write predetermined data into the memory device, and in the write operation, the memory controller selects one from the superblocks as a first target superblock of the write operation and sequentially writes a plurality of portions of the predetermined data into the pages of the first target superblock in a cyclic manner among the memory dies according to an order of the plane indices.”] [para. 0003].
Claims 13 and 19 are rejected with like reasoning.
Claims 4, 7, 11, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Muchheria et al. [hereafter as Muchheria], US Pub. No. 2021/0034274 A1 in view of Cheng [hereafter as Cheng], US Pub. No. 2024/0361934 A1 as applied to claim 1, 8, and 14 above, and further in view of Nakanishi et al. [hereafter as Nakanishi], US Pub. No. 2024/0086111 A1.
As per claim 4, Muchheria in view of Cheng discloses the memory controller of claim 1, however Muchheria and Cheng do not explicitly disclose wherein the indexer is configured to respectively assign the different indices from 1 to n to an n-number of the sub-blocks included in each of the plurality of memory blocks, based on program time information of each of the sub-blocks.
Nakanishi teaches wherein the indexer is configured to respectively assign the different indices from 1 to n to an n-number of the sub-blocks included in each of the plurality of memory blocks, based on program time information of each of the sub-blocks [“When it is determined that the write destination page is the first page (S802: YES), the sequence number assignment determination unit 215 assigns the sequence number managed as the global sequence number at that time point to the write data (S803).”] [para. 0135].
Muchheria, Cheng, and Nakanishi are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Muchheria and Cheng with Nakanishi in order to modify Muchheria and Cheng “wherein the indexer is configured to respectively assign the different indices from 1 to n to an n-number of the sub-blocks included in each of the plurality of memory blocks, based on program time information of each of the sub-blocks” as taught by Nakanishi. One of ordinary skill in the art would be motivated to combine Muchheria with Nakanishi before the effective filing date of the claimed invention to improve a system by providing where “the system write which is overhead can be significantly reduced. Therefore, the memory system 2 of the first embodiment can improve response performance to a host.” [Nakanishi, para. 0053].
Claims 11 and 17 are rejected with like reasoning.
As per claim 7, Muchheria in view of Cheng discloses the memory controller of claim 1, however Muchheria and Cheng do not explicitly disclose wherein the characteristic parameter includes at least one of a program time of each of a plurality of word-lines included in the non-volatile memory, or an average of program times of a plurality of word-lines included in each of the sub-blocks.
Nakanishi teaches wherein the characteristic parameter includes at least one of a program time of each of a plurality of word-lines included in the non-volatile memory, or an average of program times of a plurality of word-lines included in each of the sub-blocks [“When it is determined that the write destination page is the first page (S802: YES), the sequence number assignment determination unit 215 assigns the sequence number managed as the global sequence number at that time point to the write data (S803).”] [para. 0135].
Muchheria, Cheng, and Nakanishi are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Muchheria and Cheng with Nakanishi in order to modify Muchheria and Cheng “wherein the indexer is configured to respectively assign the different indices from 1 to n to an n-number of the sub-blocks included in each of the plurality of memory blocks, based on program time information of each of the sub-blocks” as taught by Nakanishi. One of ordinary skill in the art would be motivated to combine Muchheria with Nakanishi before the effective filing date of the claimed invention to improve a system by providing where “the system write which is overhead can be significantly reduced. Therefore, the memory system 2 of the first embodiment can improve response performance to a host.” [Nakanishi, para. 0053].
Claim 20 is rejected with like reasoning.
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 1 – 20 are rejected under a 112 rejection. Claims 1, 2, 4, 6 – 9, 11, 13 – 15, 17, 19, and 20 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 3, 5, 10, 12, 16, and 18 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten in independent form to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 3, 10, and 16 the prior art of record, neither anticipates, nor renders obvious a plurality of memory cells stacked on a non-volatile memory semiconductor substrate in a first direction perpendicular to the semiconductor substrate, and the position information of each of the sub-blocks includes a distance in the first direction between each of the sub-blocks and the semiconductor substrate.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 5, 12, and 18 the prior art of record, neither anticipates, nor renders obvious program time information of each of the sub-blocks includes an average of program times of a plurality of word-lines included in each of the sub-blocks.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chou et al., US Pub. No. 2022/0269443 A1 – teaches “For example, all number 0 blocks in the different dies are combined and managed as a number 0 super block, all number 1 blocks in the different dies are combined and managed as a number 1 super block, and so on.” [para. 0033]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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