DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11, 14-17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Fincato et al. (“Fincato”) (US Patent Application Publication No. 2015/0341119) in view of Nagarajan et al. (“Nagarajan”) (US Patent Application Publication No. 2005/0249509).
Regarding claim 1, Fincato discloses a circuit package comprising: a photonic integrated circuit having a first surface (fig. 1 element 1 and paragraph 0021), the photonic integrated circuit comprising a first optical modulator (figs. 1 and 2 a first one of elements 4 and paragraphs 0023 and 0027), a first detector (figs. 1 and 2 a first one of elements 6 and paragraphs 0023 and 0027), and a first optical waveguide connecting the first optical modulator and the first detector (fig. 1 a first set of elements 8 and 9 and paragraph 0024 interconnecting the first element 4 and the first element 6); a first electronic integrated circuit on the first surface, the first electronic integrated circuit being electrically coupled to control the first optical modulator (fig. 1 a first one of elements 5 and paragraph 0023 and fig. 2 and paragraph 0027); and a second electronic integrated circuit on the first surface and separated from the first electronic integrated circuit, the second electronic integrated circuit being electrically coupled to receive signals from the first detector (fig. 1 a second one of elements 5 and paragraph 0023 and fig. 2 and paragraph 0027), wherein the first electronic integrated circuit comprises a modulator driver electrically connected to the first optical modulator (Fincato: figs. 2, elements 10 and 4, and figs. 4 and 5), but does not disclose that a lateral distance between the modulator driver and the first optical modulator is smaller than 200 µm. Nagarajan discloses related integrated optical components with a lateral spacing smaller than 200 µm (fig. 8 paragraphs 0106). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a lateral spacing of 100 µm, since this suitable for minimizing electrical and thermal crosstalk, as taught by Nagarajan.
Regarding claim 2, the combination of Fincato and Nagarajan discloses the circuit package of claim 1, further comprising a second optical modulator (Fincato: figs. 1 and 2 a second one of elements 4 and paragraphs 0023 and 0027), a second detector (Fincato: figs. 1 and 2 a second one of elements 6 and paragraphs 0023 and 0027), and a second optical waveguide connecting the second optical modulator and the second detector (Fincato: fig. 1 a second set of elements 8 and 9 and paragraph 0024 interconnecting the second element 4 and the second element 6), the first electronic integrated circuit being electrically coupled to control the received signals from the second detector, and the second electronic integrated circuit being electrically coupled to control the second optical modulator (Fincato: fig. 1 the first and second ones of element 5, each transceiver circuit die 5 coupled to plural modulators 4 and detectors 6, and paragraph 0023 and fig. 2 and paragraph 0027).
Regarding claim 3, the combination of Fincato and Nagarajan discloses the circuit package of claim 2, wherein the first and second optical modulators, the first and second detectors, and the first and second optical waveguides form a bidirectional photonic channel between the first electronic integrated circuit and the second electronic integrated circuit (Fincato: fig. 1 elements 8 and 9, both plurals modulators 4 and detectors 6 each communicating between transceiver circuit dies 5 and paragraphs 0024-0025).
Regarding claim 4, the combination of Fincato and Nagarajan discloses the circuit package of claim 3, wherein the bidirectional photonic channel comprises multiple unidirectional photonic links between the first and second electronic integrated circuits in both directions (Fincato: fig. 1 elements 8 and 9 and paragraphs 0024-0025).
Regarding claim 5, the combination of Fincato and Nagarajan discloses the circuit package of claim 3, wherein the first electronic integrated circuit is a first processing element and the second electronic integrated circuit is a second processing element (Fincato: figs. 1, 2 and 5 elements 5 and paragraphs 0027-0030).
Regarding claim 6, the combination of Fincato and Nagarajan discloses the circuit package of claim 5, wherein each of the first processing element and second processing element comprises a message router including a photonic-channel interface (Fincato: fig. 2 and paragraph 0027, where the transceiver circuitry reads on message router, and is interfacing with the modulator of the photonic channel), the bidirectional photonic channel interfacing at a first end with the photonic-channel interface of the first processing element and at a second end with the photonic-channel interface of the second processing element, the circuit package being configured to optically transfer signals between the message routers of the first and second processing elements (Fincato: figs. 1 and 2, elements 8 and 9 between elements 5). Fincato does not disclose packet transfer. However, Fincato is communicating digital data (paragraphs 0001 and 0010). Further, the Office takes official notice that packetizing digital data using a standardized format, e.g., Ethernet, was conventional. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to packetize the data using a standardized format, for the benefit of interoperability with other data communications circuits and processors.
Regarding claim 7, the combination of Fincato and Nagarajan discloses the circuit package of claim 5, but does not disclose that the first processing element and the second processing element are in a single semiconductor chip. However, the difference between the combination and the claim is the plural dies, Fincato elements 5, being a single semiconductor die, which is only a manufacturing difference of making integral. Making integral is prima facie obvious when the result is merely one-piece construction, which is a matter of obvious engineering choice, that does not add anything further that would be contrary to the understandings and expectations of the art (see MPEP § 2144.04(V)(B)). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to construct the plural dies for elements 5 as a single die, since this difference is merely one-piece construction that does not add anything further that would be contrary to the understandings and expectations of the art.
Regarding claim 8, the combination of Fincato and Nagarajan discloses the circuit package of claim 1, wherein the first electronic integrated circuit and the second electronic integrated circuit are in separate semiconductor chips (Fincato: figs. 1 and 2 elements 5 and paragraphs 0012 and 0027-0030).
Regarding claim 11, the combination of Fincato and Nagarajan discloses the circuit package of claim 1, wherein the second electronic integrated circuit comprises a transimpedance amplifier with an input connected to an electrical output of the detector (Fincato: fig. 2 element 11 and paragraph 0027).
Regarding claim 14, the combination of Fincato and Nagarajan discloses the circuit package of claim 1, further comprising an optical coupling structure optically coupling the first optical waveguide to an optical fiber (Fincato: paragraph 0025).
Regarding claim 15, the combination of Fincato and Nagarajan discloses the circuit package of claim 14, wherein the optical coupling structure comprises an edge coupler (Fincato: figs. 1 and 3 and paragraph 0026, the couplers optically coupling between waveguides and the “optical I/O fiber”).
Regarding claim 16, the combination of Fincato and Nagarajan discloses the circuit package of claim 14, wherein the first optical waveguide is a portion of an optical path connecting the optical coupling structure to the first detector via the first optical modulator (Fincato: fig. 1 elements 8 and 9 connector modulators to detectors).
Regarding claim 17, the combination of Fincato and Nagarajan discloses the circuit package of claim 1, wherein the first optical modulator is an electro-absorption modulator, a Mach-Zehnder modulator, or a ring modulator (Fincato: paragraph 0023).
Regarding claim 19, the combination of Fincato and Nagarajan discloses the circuit package of claim 1, wherein the first detector is a photodiode (Fincato: paragraph 0027).
Regarding claim 20, the combination of Fincato and Nagarajan discloses the circuit package of claim 11, but does not disclose that a second lateral displacement between the transimpedance amplifier and the first detector 200 µm or less. Nagarajan discloses related integrated optical components with a lateral spacing 200 µm or less (fig. 8 paragraphs 0106). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a lateral spacing of 200 µm or less, since this suitable for minimizing electrical and thermal crosstalk, as taught by Nagarajan.
Regarding claim 21, the combination of Fincato and Nagarajan discloses the circuit package of claim 1, and discloses the connections as copper pillars with flip chip, i.e. solder bump, bonding (Fincato: paragraph 0030) but does not disclose that a vertical distance between the modulator driver and the first optical modulator is 200 pm or less. However, Nagarajan discloses related integrated optical components with a lateral spacing smaller than 200 µm (fig. 8 paragraphs 0106). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to copper pillars with flip chip, i.e. solder bump, bonding spacing of 200 µm or less, since this suitable for minimizing electrical and thermal crosstalk, as taught by Nagarajan.
Allowable Subject Matter
Claims 12 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 6 July 2026 have been fully considered but they are not persuasive. Applicant argues that Fincato teaches away from placement of optical communication links and photonic waveguide fabric silicon die “close to” electronic ICs. However, Fincato teaches “effective” separation; Fincato does not teach far from separation, or more than 200 µm separation. The argued “close to” is relative, not quantitative, and 200 µm is not inherently close to or far from, with respect to the corresponding unquantified thermal characteristics and effects. Further, Nagarajan discloses that as near as 100 µm is effective to “minimize electrical or thermal cross-talk.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN M CORS whose telephone number is (571)272-3028. The examiner can normally be reached Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Vanderpuye can be reached at 571-272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN M CORS/Primary Examiner, Art Unit 2634
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