Prosecution Insights
Last updated: August 18, 2026
Application No. 19/097,909

Network apparatus and operation method thereof having slave circuit broadcast accessing mechanism

Non-Final OA §103
Filed
Apr 02, 2025
Priority
Apr 10, 2024 — TW 113113445
Examiner
HASSAN, AURANGZEB
Art Unit
Tech Center
Assignee
Realtek Semiconductor Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
1y 6m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
618 granted / 770 resolved
+20.3% vs TC avg
Strong +17% interview lift
Without
With
+17.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
24 currently pending
Career history
793
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
56.3%
+16.3% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 770 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claims 1 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Publication Number 2015/0339253, hereinafter “Chen”) in view Rumpler et al. (US Publication Number 2021/0240656, hereinafter “Rumpler”). 4. As per claims 1 and 8, Chen teaches a network apparatus and method having a slave circuit broadcast accessing mechanism (figure 5, MDIO master 402 and MDIO slave 504), comprising: a plurality of lower layer slave circuits each having a device address independent from each other (plurality of MDIO slaves 504, figure 5, having mutually independent designated PHY addresses 0x1…3, paragraph 35); and an upper layer master circuit electrically coupled to the lower layer slave circuits to perform network communication through the lower layer slave circuits (STA paragraph 25 embedded in the MAC layer acts as master MMD embedded in the PHY device acts as slave, 502 and 504, figure 5); the upper layer master circuit (STA/MDIO master 502, figure 5 generates and transmits the commands) configured to: and transmit a broadcast mode read command comprising the broadcast address to the lower layer slave circuits (a command carrying an address matching only one slaves setting activates the single slave, paragraphs 37 – 38). Chen does not appear to explicitly disclose transmit a broadcast mode activation command comprising a broadcast address to the lower layer slave circuits to configure each of the lower layer slave circuits to have the broadcast address such that the lower layer slave circuits enter a broadcast mode; transmit a broadcast mode write command comprising the broadcast address and broadcast write data to the lower layer slave circuits such that the lower layer slave circuits configured to have the broadcast address perform data writing according to the broadcast write data; such that only one of the lower layer slave circuits having the device address matching the broadcast address performs data reading and returns individual read data. However, Rumpler discloses transmit a broadcast mode activation command comprising a broadcast address to the lower layer slave circuits (master sequentially transmits a write command that writes in a broadcast mode bit into a register of each slave, activating broadcast mode, figure 4, step 402, figure 7 enable bit 720, paragraphs 28 – 31) to configure each of the lower layer slave circuits to have the broadcast address such that the lower layer slave circuits enter a broadcast mode (paragraph 28 – 31, writing the broadcast mode bit configures each slave to respond to the broadcast address and enter the broadcast mode, figure 7); transmit a broadcast mode write command comprising the broadcast address and broadcast write data to the lower layer slave circuits (paragraphs 32 – 34, with all slaves in broadcast mode, the master simultaneously writes the same data to all slaves, step 404, figure 4, and figure 6) such that the lower layer slave circuits configured to have the broadcast address perform data writing according to the broadcast write data (paragraphs 32 – 34, all slaves in broadcast mode are programmed with the same data); such that only one of the lower layer slave circuits having the device address matching the broadcast address performs data reading and returns individual read data (paragraphs 24 – 26, and 44, simultaneous drive of the shared response line by two slaves causes a bus error and the response driver in broadcast mode is disabled/controlled so that only one slave drives the response line and returns own read data). Chen and Rumpler are analogous art because they are from the same field of endeavor of a single master handling configuration of a plurality of slaves. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen and Rumpler before him or her, to modify the structure of Chen to include the trigger management of Rumpler because it would enhance the master functionality more explicitly allowing for control of slaves. One of ordinary skill would be motivated to make such modification in order to enhance master functionality of slaves utilized a shared bus (paragraphs 4 – 7). Therefore, it would have been obvious to combine Rumpler with Chen to obtain the invention as specified in the instant claims. 5. Chen modified by the teachings of Rumpler as seen in claim 1 above, as per claims 2 and 9, Chen teaches an apparatus and method, wherein the broadcast address is configured to be the device address of one of the lower layer slave circuits (figure 5, the predefined address setting gid = 0x1e is held by slaves 504_1 and 5-4_3 and gid=0x1d is held by slave 504_2, the broadcast group address is configured to be the device address of a particular slave, paragraphs 35 – 39) . 6. Chen modified by the teachings of Rumpler as seen in claim 1 above, as per claims 3 and 10, Chen teaches an apparatus and method, wherein the device address of each of the lower layer slave circuits is a sum of a base address and a device identification number (slaves assigned sequential designated PHY addresses a base value offset by a device identification number up to 32 addressable PHY devices per master, paragraph 35). 7. Chen modified by the teachings of Rumpler as seen in claim 1 above, as per claims 4 and 11, Chen teaches an apparatus and method, wherein each of the lower layer slave circuits is a physical layer (PHY) circuit, and the upper layer master circuit is a media access control (MAC) circuit (the STA, paragraph 25 is embedded in the MAC layer and acts as a master for the MDIO interface and MMD is embedded in the PHY device and acts as a slave on the MDIO interface, figure 1). 8. Chen modified by the teachings of Rumpler as seen in claim 1 above, as per claims 5 and 12, Chen teaches an apparatus and method, wherein the lower layer slave circuits and the upper layer master circuit perform communication through a serial management interface (SMI) (management data input/out MDIO, paragraph 3) such that each of the lower layer slave circuits serves as a serial management interface slave and the upper layer master circuit serves as a serial management interface master (MDIO master is the STA, paragraph 25, MDIO slave is MMD, paragraph 3, bus 501 connecting master 502 to slaves 504_1…3, figure 5). 9. Chen modified by the teachings of Rumpler as seen in claim 1 above, as per claims 6 and 13, Rumpler teaches an apparatus and method, wherein the upper layer master circuit is further configured to transmit a broadcast mode deactivation command to the lower layer slave circuits (paragraphs 35 – 38, after simultaneous broadcast write the master issues a write command to de-assert the broadcast mode bit in each slave, the mode also disabled automatically at the end of command or timer, figure 4, step 406, figure 7, bit 720) such that the lower layer slave circuits remove the configuration of the broadcast address to enter a non-broadcast mode (paragraphs 35 – 38, de-asserting mode bit removed broadcast configuration and returns the slave to non-broadcast individually addressed operation). 10. Chen modified by the teachings of Rumpler as seen in claim 1 above, as per claims 7 and 14, Chen teaches an apparatus and method, wherein when the lower layer slave circuits enter the non-broadcast mode, the upper layer master circuit is configured to (read write command for particular PHY address is executed by only one MDIO slave, paragraphs 4 and 53): transmit a non-broadcast mode write command comprising a write address and write data to the lower layer slave circuits such that one of the lower layer slave circuits having the device address matching the write address performs data writing according to the write data (figures 9 and 10, MDIO master transmits write data to the individually addressed slave per the wrote command, figure 9 steps 902 to 904); and transmit a non-broadcast mode read command comprising a read address to the lower layer slave circuits such that one of the lower layer slave circuits having the device address matching the read address performs data reading and returns read data (MDIO master receives read data from the individually addressed slave per read command figure 10, paragraphs 54 – 56). Conclusion 11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fay/Mishra/Nakanishi/Srivastava have master slave addressing techniques via broadcast for individualized handling. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AH /HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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Prosecution Timeline

Apr 02, 2025
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
97%
With Interview (+17.0%)
2y 10m (~1y 6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 770 resolved cases by this examiner. Grant probability derived from career allowance rate.

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