780DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 75-78 and 80-90 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of U.S. Patent No. 11,658,673. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims are anticipated by the patented claims – claims are reproduced in a table below for comparison.
Claim No.: __ of Application 19/098,605
Claim No.: __ of USP 11,658,673
75. Monitoring circuitry configured to receive a supply voltage applied to digital circuitry and an input signal for the digital circuitry, the monitoring circuitry configured to generate a modified input signal for the digital circuitry based on the input signal and the supply voltage.
1. Circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage; wherein the monitoring circuitry is configured to receive an input signal for the digital circuitry and to output a modified input signal to the digital circuitry as the control signal, and wherein the digital circuitry is configured to generate the digital output signal based on the modified input signal.
76. The monitoring circuitry of claim 75, wherein the monitoring circuitry comprises: waveform generator circuitry configured to generate a voltage having an amplitude that changes over time based on a magnitude of the supply voltage; comparator circuitry configured to compare the voltage to a reference voltage and to output a comparison signal when the voltage reaches the reference voltage; and logic circuitry configured to receive the input signal and the comparison signal and to generate the modified input signal for the digital circuitry based on the input signal and the comparison signal.
4. Circuitry according to claim 1, wherein the monitoring circuitry comprises: waveform generator circuitry configured to generate a voltage having an amplitude that changes over time based on a magnitude of the supply voltage; comparator circuitry configured to compare the voltage to a reference voltage and to output a comparison signal when the voltage reaches the reference voltage; and logic circuitry configured to receive the input signal and the comparison signal and to generate the modified input signal for the digital circuitry based on the input signal and the comparison signal.
77. The monitoring circuitry of claim 76, wherein the waveform generator circuitry is configured such that a rate of increase of the voltage is inversely proportional to the magnitude of the supply voltage.
4. “…waveform generator circuitry configured to generate a voltage having an amplitude that changes over time based on a magnitude of the supply voltage”
78. The monitoring circuitry of claim 76, wherein the waveform generator circuitry is configured to generate a ramp voltage.
4. “…waveform generator circuitry configured to generate a voltage having an amplitude that changes over time based on a magnitude of the supply voltage”
80. The monitoring circuitry of claim 76, wherein the monitoring circuitry comprises: analogue-to-digital converter (ADC) circuitry configured to generate a digital output signal based on the supply voltage; timer circuitry configured to: receive the input signal and the digital output signal; commence timing a time period on detection of a feature of the input signal, wherein a duration of the time period is based on the digital output signal; and output a timer output signal at the end of the time period; and logic circuitry configured to receive the input signal and the timer output signal and to generate the modified input signal for the digital circuitry based on the input signal and the timer output signal.
5. Circuitry according to claim 1, wherein the monitoring circuitry comprises: analogue-to-digital converter (ADC) circuitry configured to generate a digital output signal based on the supply voltage; timer circuitry configured to: receive the input signal and the digital output signal; commence timing a time period on detection of a feature of the input signal, wherein a duration of the time period is based on the digital output signal; and output a timer output signal at the end of the time period; and logic circuitry configured to receive the input signal and the timer output signal and to generate a modified input signal for the digital circuitry based on the input signal and the timer output signal.
81. The monitoring circuitry of claim 80, wherein the timer circuitry is configured such that the duration of the time period is inversely proportional to a magnitude of the supply voltage.
5. “… analogue-to-digital converter (ADC) circuitry configured to generate a digital output signal based on the supply voltage; timer circuitry configured to: receive the input signal and the digital output signal; commence timing a time period on detection of a feature of the input signal, wherein a duration of the time period is based on the digital output signal”
82. The monitoring circuitry according of claim 80, wherein the feature of the input signal is a rising edge of a pulse of the input signal.
5. “…timer circuitry configured to: receive the input signal and the digital output signal; commence timing a time period on detection of a feature of the input signal”
83. The monitoring circuitry of claim 76, wherein the monitoring circuitry comprises: voltage controlled oscillator (VCO) circuitry configured to generate an oscillating output signal having a frequency that is based on the supply voltage; counter circuitry configured to: receive the input signal and the oscillating output signal; commence a count of cycles of the oscillating signal on detection of a feature of the input signal; and output a counter output signal when the count reaches a count value that represents a magnitude of the supply voltage; and logic circuitry configured to receive the input signal and the counter output signal and to generate the modified input signal for the PWM circuitry based on the input signal and the timer output signal.
6. Circuitry according to claim 1, wherein the monitoring circuitry comprises: voltage controlled oscillator (VCO) circuitry configured to generate an oscillating output signal having a frequency that is based on the supply voltage; counter circuitry configured to: receive the input signal and the oscillating output signal; commence a count of cycles of the oscillating signal on detection of a feature of the input signal; and output a counter output signal when the count reaches a count value that represents a magnitude of the supply voltage; and logic circuitry configured to receive the input signal and the counter output signal and to generate a modified input signal for the PWM circuitry based on the input signal and the timer output signal.
84. The monitoring circuitry of claim 83, wherein the VCO circuitry is configured such that the frequency of the oscillating output signal is inversely proportional to a magnitude of the supply voltage.
6. “wherein the monitoring circuitry comprises: voltage controlled oscillator (VCO) circuitry configured to generate an oscillating output signal having a frequency that is based on the supply voltage”
85. The monitoring circuitry of claim 83, wherein the feature of the input signal is a rising edge of a pulse of the input signal.
6. “…commence a count of cycles of the oscillating signal on detection of a feature of the input signal”
86. Digital driver circuitry comprising: digital output circuitry; and monitoring circuitry, wherein the monitoring circuitry is configured to receive an input signal for the digital output circuitry and a supply voltage applied to the digital output driver circuitry and to generate a modified input signal for the digital output circuitry based on the input signal and the supply voltage.
1. Circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage; wherein the monitoring circuitry is configured to receive an input signal for the digital circuitry and to output a modified input signal to the digital circuitry as the control signal, and wherein the digital circuitry is configured to generate the digital output signal based on the modified input signal.
87. The digital driver circuitry of claim 86, wherein the digital output circuitry is configured to generate a digital output signal based on the modified input signal.
1. “…wherein the digital circuitry is configured to generate the digital output signal based on the modified input signal”
88. The digital driver circuitry of claim 86, wherein the digital output circuitry comprises pulse width modulation circuitry configured to generate a pulse width modulated (PWM) output signal based on the modified input signal.
1. “… wherein the monitoring circuitry is configured to receive an input signal for the digital circuitry and to output a modified input signal to the digital circuitry as the control signal, and wherein the digital circuitry is configured to generate the digital output signal based on the modified input signal.” and 3. “…wherein the digital circuitry is operative to control a pulse width of a pulse of the digital output signal based on the control signal”
89. The digital driver circuitry of claim 88, wherein a pulse width of a pulse of the PWM output signal is dependent on the modified input signal.
3. “…wherein the digital circuitry is operative to control a pulse width of a pulse of the digital output signal based on the control signal”
90. The digital driver circuitry of claim 88, wherein the monitoring circuitry is configured to generate the modified input signal such that a change in the supply voltage is compensated by a change in the pulse width of the pulse of the PWM output signal.
1. “…monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage; wherein the monitoring circuitry is configured to receive an input signal for the digital circuitry and to output a modified input signal to the digital circuitry as the control signal”
Allowable Subject Matter
Claim 79 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 91-92 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 79, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “said the monitoring circuitry comprises: a capacitor; voltage-to-current converter circuitry configured to generate a first current based on the supply voltage; current generator circuitry configured to generate a constant current for charging the capacitor; current mirror circuitry; and a current control transistor, wherein the current mirror circuitry is configured to mirror the first current to a control terminal of the current control transistor, such that the current control transistor controls a portion of the constant current that is diverted away from the capacitor” is not found in the prior art of record.
Regarding claims 91-92, the prior art of record, when taken alone or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged or provided in the manner as claimed by the applicant. Added for emphasis, the claim recitation “said circuitry is configured to condition, control or adjust a width of one or more digital pulses to compensate for changes in a supply voltage supplied to a digital modulator of the circuitry in order to maintain a consistent average voltage per period of the digital signal for a given load condition” is not found in the prior art of record.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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