DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 04/02/2025.
Claims 1-25 are pending.
Claims 1-5, 7-15, and 17-25 are rejected.
Claims 6 and 16 are objected to.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims 7 and 17. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the rejections provided herein which must be addressed accordingly.
Priority
Applicant’s priority claim to provisional US Application 63/635,985 filed 04/18/2025 is herein acknowledged.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 08/19/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 04/02/2025 are acceptable for examination purposes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 17, 23-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 7 recites “update the second firmware image, the third firmware image, the fourth firmware image, and the fifth firmware image with data associated with the command; and store placeholder data to one or more of the first plane, the second plane, the third plane, and the fourth plane based at least in part on updating the second firmware image, the third firmware image, the fourth firmware image, and the fifth firmware image.” It is unclear as to the relationship between storing the “placeholder data” and updating the firmware images as to whether the storing of the placeholder data occurs after each update step or after the collective performance of the updating of each of the second, third, fourth, and fifth firmware images. Additionally, it is unclear as to whether the update of the firmware images utilizes the placeholder data or if the placeholder data is considered as distinct data stored during the update process. Furthermore, it is unclear as to which plane the placeholder data is stored. The Examiner notes MPEP § 2111.01(II) wherein it is detailed to be improper to import limitations into the claims from the Specification.
Claim 17 recites the same issue as identified for claim 7.
Claim 23 recites “reading, based at least in part on determining that the first firmware image satisfies the error threshold, a second firmware image…” wherein the recitation of satisfying the error threshold is not consistent with the limitation as supported by the Specification, as presented in Paragraph [0058], which details reading the second firmware image as being based on determining the first firmware image does not satisfy the error threshold. Claims 3 and 13 recite similar limitations wherein this is the case. Claim 24 depends on claim 23 and does not resolve the issue. For purposes of the current action and compact prosecution, it is interpreted for the limitation to be consistent with the originally filed Specification as supported to recite the number of errors as not satisfying the error threshold.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5, 8-11, 15, 18-21, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello (US 2022/0107899) in view of Zimmer et al. (US 2015/0271297).
Regarding claim 1, Cariello discloses, in the italicized portions, a memory device, comprising: one or more memory arrays ([0024] In some cases, memory device 100 may include a three-dimensional (3D) memory array, where multiple two-dimensional (2D) memory arrays are formed on top of one another.); and processing circuitry coupled with the one or more memory arrays and configured to cause the memory device to ([0030] In some examples, the memory controller 155 may retrieve firmware code (or “firmware,” “firmware data”) from a set of memory cells 105 as part of a start-up procedure.): transition, by the memory device, from a first power state to a second power state, wherein transitioning from the first power state to the second power state occurs during a boot operation; read, based at least in part on transitioning from the first power state to the second power state, a first firmware image that is stored to two or more planes of the memory device; and operate, based at least in part on reading the first firmware image, the memory device according to the first firmware image ([0030] The firmware code may be low-level code (e.g., operating code) that enables the memory controller 155 to subsequently perform higher-level functions using more complex software. Multiple copies of the firmware code may be stored within memory device 100, which may provide redundancy and increased reliability, among other benefits. [0049] In some examples, different memory planes may store respective copies of firmware. For example, a first memory plane (e.g., plane 0) may store a first copy of firmware, a second memory plane (e.g., plane 1) may store a second copy of the firmware, a third plane (e.g., plane 2) may store a third copy of the firmware, and a fourth plane (e.g., plane 3) may store a fourth copy of the firmware.). Herein Cariello discloses a memory device comprising a memory array which includes a plurality of memory planes wherein a plurality of copies of firmware are respectively stored per plane. Firmware code is then retrieved by the memory controller for execution as part of a start-up procedure from a memory plane or planes. Cariello does not explicitly disclose that reading the firmware is done is response to a transition of the memory device from a first power state to a second power state during the boot operation. Regarding this aspect of the limitation, Zimmer discloses in Paragraphs [0035-36] “[0035] Referring now to FIG. 4, in use, a client device 104 may execute a boot process 400 according to the UEFI specification. The boot process 400 may be executed whenever the client device 104 is powered on, including when the client device 104 is powered on from a full electrical or mechanical "off" state, when the client device 104 is powered from a "soft-off" power state, when the client device 104 is reset or rebooted, or when the client device 104 is awoken from a sleep state. [0036] In block 404, the client device 104 loads and starts firmware images for one or more firmware drivers 406 or firmware applications 408. Firmware drivers 406 and firmware applications 408 are binary images that may be stored in a system partition of the data storage device 146. The particular drivers and applications to be loaded are platform-dependent and may be enumerated in global variables of the client device 104, for example, in platform flash memory of the client device 104.” Herein Zimmer discloses as part of the boot process, which occurs in response to a power state change from either a full off state or soft off state to a powered on state, the process executes loading the execution of firmware images retrieved from storage. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the boot process as recited in Cariello may include power state transitions as discussed in Zimmer in order to prompt and execute the firmware image retrieval and execution for operation of the memory device. Cariello and Zimmer are analogous art because they are from the same field of endeavor of boot firmware management.
Regarding claim 5, Cariello and Zimmer in combination further disclose the memory device of claim 1, wherein the two or more planes comprise a first plane, a second plane, a third plane, and a fourth plane, a second firmware image is stored to the first plane, a third firmware image is stored to the second plane, a fourth firmware image is stored to the third plane, and a fifth firmware image is stored to the fourth plane (Cariello [0049] In some examples, different memory planes may store respective copies of firmware. For example, a first memory plane (e.g., plane 0) may store a first copy of firmware, a second memory plane (e.g., plane 1) may store a second copy of the firmware, a third plane (e.g., plane 2) may store a third copy of the firmware, and a fourth plane (e.g., plane 3) may store a fourth copy of the firmware.). Herein Cariello explicitly disclose the storage of respective firmware copies to a first, second, third, and fourth plane.
Regarding claim 8, Cariello and Zimmer in combination further disclose the memory device of claim 5, wherein the first firmware image, the second firmware image, the third firmware image, the fourth firmware image, and the fifth firmware image comprise identical data (Cariello [0048] For functionality and reliability reasons a memory device may store multiple copies (e.g., identical copies) of firmware code.). Herein Cariello explicitly discloses the copies can be identical copies of the firmware which therefore comprise identical data.
Regarding claim 9, Cariello and Zimmer in combination further disclose the memory device of claim 1, wherein the first firmware image is stored to a first plane, a second plane, a third plane, and a fourth plane of the two or more planes (Cariello [0049]), wherein to read the first firmware image the processing circuitry configured to cause the memory device to: read a first portion of the first firmware image from the first plane; read, based at least in part on reading the first portion of the first firmware image from the first plane, a second portion of the first firmware image from the second plane; read, based at least in part on reading the second portion of the first firmware image from the second plane, a third portion of the first firmware image from the third plane; and read, based at least in part on reading the third portion of the first firmware image from the third plane, a fourth portion of the first firmware image from the fourth plane (Cariello [0054] Firmware layout 400-b may enable concurrent reading of multiple subsets of firmware code by staggering the page address of the pages used to store a given subset of firmware code for different copies. For example, page 4 may store the first subset (e.g., subset 0) of firmware code for the copy in plane 0, whereas page 3 may store the first subset (e.g., subset 0) of firmware code for the copy in plane 1. And so on and so forth. By storing like subsets of different copies of the firmware code in pages having offset (different) page addresses, the memory device may enable a parallel retrieval method in which different subsets of firmware code are read concurrently from pages within different memory planes. In some examples, a memory device implementing the parallel retrieval method may be referred to as operating in multi-plane mode. [0055] As an example of the parallel retrieval method, the following read operations may be performed concurrently: a first read operation to read a first subset of firmware code (e.g., set 0) from page 4 in plane 0, a second read operation to read a second subset of firmware code (e.g., set 1) from page 4 in plane 1, a third read operation to read a third subset of firmware code (e.g., set 2) from page 4 in plane 2, and a fourth read operation to read a fourth subset of firmware code (e.g., set 3) from page 4 in plane 3.). Herein Cariello explicitly identifies performing a parallel retrieval method where firmware data from the plurality of planes may be accessed. In this manner, a respective portion of the first firmware image which is stored as copies to each of the plurality of planes may be retrieved from each plane.
Regarding claim 10, Cariello and Zimmer in combination further disclose the memory device of claim 1, wherein the first firmware image is stored to at least a first plane, a second plane, a third plane, and a fourth plane of the memory device (Cariello [0049]), and wherein the first plane and the second plane are each associated with a first memory die and the third plane and the fourth plane are each associated with a second memory die (Cariello [0043] Although shown with a single memory die 320 for the sake of clarity, memory device 300 may in some cases include multiple memory dies 320, and each memory die 320 may be configured to independently execute commands or report status. In some cases, there may be independent operation registers, status indication signals, and/or external signal lines shared within memory dies 320. A memory die 320 may include (e.g., be logically divided into) one or more memory planes 325, which may share one or more operation registers so that memory device 300 can perform concurrent (e.g., identical) operations on multiple planes 325. [0088] In some examples of the method 700 and the apparatus described herein, the first and second planes are within a same memory die.). Herein Cariello disclose the configuration of the memory device as storing the firmware image to the plurality of planes and that a plurality of memory dies may be present in the device and respectively divided into a plurality of planes wherein, for example, a single die may comprise two planes. In this manner, it would be obvious to one of ordinary skill in the art to configure a second die of the plurality of dies to comprise the third and fourth planes as claimed.
Regarding claim 11, Cariello discloses, in the italicized portions, a non-transitory computer-readable medium storing code, the code comprising instructions which, when executed by one or more processors of a memory device ([0082] In some examples, an apparatus as described herein may perform a method or methods, such as the method 700. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for reading a first subset of a set of firmware code from a first page of memory.), cause the memory device to: transition, by the memory device, from a first power state to a second power state, wherein transitioning from the first power state to the second power state occurs during a boot operation; read, based at least in part on transitioning from the first power state to the second power state, a first firmware image that is stored to two or more planes of the memory device; and operate, based at least in part on reading the first firmware image, the memory device according to the first firmware image ([0030] and [0049]). Herein Cariello discloses a memory device comprising a memory array which includes a plurality of memory planes wherein a plurality of copies of firmware are respectively stored per plane. Firmware code is then retrieved by the memory controller for execution as part of a start-up procedure from a memory plane or planes. Cariello does not explicitly disclose that reading the firmware is done is response to a transition of the memory device from a first power state to a second power state during the boot operation. Regarding this aspect of the limitation, Zimmer discloses in Paragraphs [0035-36] as part of the boot process, which occurs in response to a power state change from either a full off state or soft off state to a powered on state, the process executes loading the execution of firmware images retrieved from storage. Claim 11 is rejected on a similar basis as claim 1.
Regarding claim 15, Cariello and Zimmer in combination further disclose the non-transitory computer-readable medium of claim 11, wherein the two or more planes comprise a first plane, a second plane, a third plane, and a fourth plane, a second firmware image is stored to the first plane, a third firmware image is stored to the second plane, a fourth firmware image is stored to the third plane, and a fifth firmware image is stored to the fourth plane (Cariello [0049]). Claim 15 is rejected on a similar basis as claim 5.
Regarding claim 18, Cariello and Zimmer in combination further disclose the non-transitory computer-readable medium of claim 15, wherein the first firmware image, the second firmware image, the third firmware image, the fourth firmware image, and the fifth firmware image comprise identical data (Cariello [0048]). Claim 18 is rejected on a similar basis as claim 8.
Regarding claim 19, Cariello and Zimmer in combination further disclose the non-transitory computer-readable medium of claim 11, wherein the first firmware image is stored to a first plane, a second plane, a third plane, and a fourth plane of the two or more planes (Cariello [0049]), wherein the instructions to read the first firmware image, when executed by the one or more processors of the memory device, further cause the memory device to: read a first portion of the first firmware image from the first plane; read, based at least in part on reading the first portion of the first firmware image from the first plane, a second portion of the first firmware image from the second plane; read, based at least in part on reading the second portion of the first firmware image from the second plane, a third portion of the first firmware image from the third plane; and read, based at least in part on reading the third portion of the first firmware image from the third plane, a fourth portion of the first firmware image from the fourth plane (Cariello [0054-55]). Claim 19 is rejected on a similar basis as claim 9.
Regarding claim 20, Cariello and Zimmer in combination further disclose the non-transitory computer-readable medium of claim Il, wherein the first firmware image is stored to at least a first plane, a second plane, a third plane, and a fourth plane of the memory device (Cariello [0049]), and wherein the first plane and the second plane are each associated with a first memory die and the third plane and the fourth plane are each associated with a second memory die (Cariello [0043]). Claim 20 is rejected on a similar basis as claim 10.
Regarding claim 21, Cariello discloses, in the italicized portions, a method by a memory device (Figure 7, [0078] method for supporting firmware loading), comprising: transitioning, by the memory device, from a first power state to a second power state, wherein transitioning from the first power state to the second power state occurs during a boot operation; reading, based at least in part on transitioning from the first power state to the second power state, a first firmware image that is stored to two or more planes of the memory device; and operating, based at least in part on reading the first firmware image, the memory device according to the first firmware image ([0030] and [0049]). Herein Cariello discloses a memory device comprising a memory array which includes a plurality of memory planes wherein a plurality of copies of firmware are respectively stored per plane. Firmware code is then retrieved by the memory controller for execution as part of a start-up procedure from a memory plane or planes. Cariello does not explicitly disclose that reading the firmware is done is response to a transition of the memory device from a first power state to a second power state during the boot operation. Regarding this aspect of the limitation, Zimmer discloses in Paragraphs [0035-36] as part of the boot process, which occurs in response to a power state change from either a full off state or soft off state to a powered on state, the process executes loading the execution of firmware images retrieved from storage. Claim 21 is rejected on a similar basis as claim 1.
Regarding claim 25, Cariello and Zimmer in combination further disclose the method of claim 21, wherein the two or more planes comprise a first plane, a second plane, a third plane, and a fourth plane, and wherein a second firmware image is stored to the first plane, a third firmware image is stored to the second plane, a fourth firmware image is stored to the third plane, and a fifth firmware image is stored to the fourth plane (Cariello [0049]). Claim 25 is rejected on a similar basis as claim 5.
Claims 2-4, 12-14, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello in view of Zimmer and further in view of Gyllenskog (US 2020/0183594).
Regarding claim 2, Cariello and Zimmer do not explicitly disclose the memory device of claim 1, wherein the processing circuitry is further configured to cause the memory device to: determine, based at least in part on reading the first firmware image, whether the first firmware image contains an error, wherein operating the memory device according to the first firmware image is based at least in part on determining that the first firmware image satisfies an error threshold. Regarding this limitation, Gyllenskog discloses in Paragraph [0014] “When the memory subsystem determines that the first copy of the firmware has a number of bit errors that exceeds the correctable threshold number of errors, the memory subsystem reads a second copy of the firmware that is also stored in the memory components. The memory subsystem again checks/corrects for bit errors to determine whether the number of bit errors in the second copy of the firmware exceeds the correctable threshold number of bit errors. When the memory subsystem determines that the second copy of the firmware has a number of bit errors that is less than or equal to the correctable threshold number of errors, the memory subsystem corrects for any bit errors and loads the second copy of the firmware into main memory.” Herein Gyllenskog discloses that it is determined whether a read firmware from memory contains an error threshold number of errors and whether or not to utilize the firmware based on the number of errors being below the threshold. Furthermore, the memory stores multiple copies of the firmware which may be loaded based on determining the number of errors exceeding the threshold for a respective copy. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the number of errors would be determined in order to avoid reading invalid data and to determine when to access the additional copies of the firmware as is similarly maintained in Cariello and Zimmer to ensure proper performance of the memory device (Gyllenskog [0013]). Cariello, Zimmer, and Gyllenskog are analogous art because they are from the same field of endeavor of boot firmware management.
Regarding claim 3, Cariello, Zimmer, and Gyllenskog in combination further disclose the memory device of claim 2, wherein the processing circuitry is further configured to cause the memory device to: read, based at least in part on determining that the first firmware image does not satisfy the error threshold, a second firmware image that is stored to a first plane of the memory device; and operate, based at least in part on reading the second firmware image, the memory device according to the second firmware image (Gyllenskog [0014]). As is similarly presented in the rejection of claim 2, Gyllenskog explicitly discloses reading from a second copy of firmware when the first read copy is determined to have a number of errors exceeding a threshold. In this scenario, the number of errors exceeding the threshold is determined to be analogous to the limitation of determining to not satisfying the error threshold. In view of Zimmer, this second copy may be stored to a different plane than the first copy.
Regarding claim 4, Cariello, Zimmer, and Gyllenskog in combination further disclose the memory device of claim 3, wherein the processing circuitry is further configured to cause the memory device to: determine, based at least in part on reading the second firmware image, that the second firmware image does not satisfy the error threshold; read, based at least in part on determining that the second firmware image does not satisfy the error threshold, a third firmware image that is stored to a second plane of the memory device; and operate, based at least in part on reading the third firmware image, the memory device according to the third firmware image (Gyllenskog [0014] Although described in relation to two copies of the firmware, the process of finding a useable/acceptable copy of the firmware could require reading and refreshing more than two copies of the firmware.). Herein Gyllenskog explicitly notes that more iterations of the loading of firmware and determination of errors beyond two cycles may be performed. In view of Cariello wherein firmware of up to at least four copies to four different planes is disclosed, it would be obvious to one of ordinary skill in the art to access a third firmware image in a second plane as claimed.
Regarding claim 12, Cariello and Zimmer do not explicitly disclose the non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the one or more processors of the memory device, further cause the memory device to: determine, based at least in part on reading the first firmware image, whether the first firmware image contains an error, wherein operating the memory device according to the first firmware image is based at least in part on determining that the first firmware image satisfies an error threshold. Regarding this limitation, Gyllenskog discloses in Paragraph [0014] that it is determined whether a read firmware from memory contains an error threshold number of errors and whether or not to utilize the firmware based on the number of errors being below the threshold. Furthermore, the memory stores multiple copies of the firmware which may be loaded based on determining the number of errors exceeding the threshold for a respective copy. Claim 12 is rejected on a similar basis as claim 2.
Regarding claim 13, Cariello, Zimmer, and Gyllenskog in combination further disclose the non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the one or more processors of the memory device, further cause the memory device to: read, based at least in part on determining that the first firmware image does not satisfy the error threshold, a second firmware image that is stored to a first plane of the memory device; and operate, based at least in part on reading the second firmware image, the memory device according to the second firmware image (Gyllenskog [0014]). Gyllenskog explicitly discloses reading from a second copy of firmware when the first read copy is determined to have a number of errors exceeding a threshold. In this scenario, the number of errors exceeding the threshold is determined to be analogous to the limitation of determining to not satisfying the error threshold. In view of Zimmer, this second copy may be stored to a different plane than the first copy.
Regarding claim 14, Cariello, Zimmer, and Gyllenskog in combination further disclose the non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the one or more processors of the memory device, further cause the memory device to: determine, based at least in part on reading the second firmware image, that the second firmware image does not satisfy the error threshold; read, based at least in part on determining that the second firmware image does not satisfy the error threshold, a third firmware image that is stored to a second plane of the memory device; and operate, based at least in part on reading the third firmware image, the memory device according to the third firmware image (Gyllenskog [0014] Although described in relation to two copies of the firmware, the process of finding a useable/acceptable copy of the firmware could require reading and refreshing more than two copies of the firmware.). Herein Gyllenskog explicitly notes that more iterations of the loading of firmware and determination of errors beyond two cycles may be performed. Claim 14 is rejected on a similar basis as claim 4.
Regarding claim 22, Cariello and Zimmer do not explicitly disclose the method of claim 21, further comprising: determining, based at least in part on reading the first firmware image, whether the first firmware image contains an error, wherein operating the memory device according to the first firmware image is based at least in part on determining that the first firmware image satisfies an error threshold. Regarding this limitation, Gyllenskog discloses in Paragraph [0014] that it is determined whether a read firmware from memory contains an error threshold number of errors and whether or not to utilize the firmware based on the number of errors being below the threshold. Furthermore, the memory stores multiple copies of the firmware which may be loaded based on determining the number of errors exceeding the threshold for a respective copy. Claim 22 is rejected on a similar basis as claim 2.
Regarding claim 23, Cariello, Zimmer, and Gyllenskog in combination further disclose the method of claim 22, further comprising: reading, based at least in part on determining that the first firmware image satisfies the error threshold, a second firmware image that is stored to a first plane of the memory device; and operating, based at least in part on reading the second firmware image, the memory device according to the second firmware image (Gyllenskog [0014]). Gyllenskog explicitly discloses reading from a second copy of firmware when the first read copy is determined to have a number of errors exceeding a threshold. In this scenario, the number of errors exceeding the threshold is determined to be analogous to the limitation of determining to satisfying the error threshold. As noted previously, for the current action it is interpreted that the limitation is to be presented in the manner by which the Specification supports the recitation of the number of errors exceeding the threshold as not satisfying the threshold. In view of Zimmer, this second copy may be stored to a different plane than the first copy.
Regarding claim 24, Cariello, Zimmer, and Gyllenskog in combination further disclose the method of claim 23, further comprising: determining, based at least in part on reading the second firmware image, that the second firmware image does not satisfy the error threshold; reading, based at least in part on determining that the second firmware image does not satisfy the error threshold, a third firmware image that is stored to a second plane of the memory device; and operating, based at least in part on reading the third firmware image, the memory device according to the third firmware image (Gyllenskog [0014] Although described in relation to two copies of the firmware, the process of finding a useable/acceptable copy of the firmware could require reading and refreshing more than two copies of the firmware.). Herein Gyllenskog explicitly notes that more iterations of the loading of firmware and determination of errors beyond two cycles may be performed. The Examiner notes the difference in language between claims 23 and 24, wherein claim 24 depends from claim 23, and the presentation of reading a subsequent firmware image in response to determining the satisfaction of an error threshold and that in claim 23 the second firmware image is recited to be read upon determining the first image does satisfy the error threshold and in claim 24 that the third firmware image is read when the second firmware image does not satisfy the error threshold. For the current action as noted previously, the disclosure of the cited prior art references are determined to teach the claimed limitations regarding the scope which is supported by the originally filed Specification pertaining to not satisfying the threshold in order to perform the next step of reading the next firmware image.
Allowable Subject Matter
Claims 6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 recites the following limitations: “receive, from a host system, a command indicating an update to the first firmware image; program, based at least in part on receiving the command, the second firmware image and the fifth firmware image; transition, by the memory device and based at least in part on programming the second firmware image and the fifth firmware image, from the second power state to the first power state and back to the second power state; program, based at least in part on transitioning back to the second power state, the third firmware image and the fourth firmware image; and program the first firmware image based at least in part on programming the second firmware image, the third firmware image, the fourth firmware image, and the fifth firmware image.” Herein the claim limitations require the ordering of programming the plurality of firmware images in response to an update command, including a power state transition after programming the second and fifth firmware images. The prior art of record of closest relevance, Cariello and Baik, disclose techniques for updating firmware images stored to planes. However, the prior art references of record fail to disclose the particular ordering of steps for updating the planes as claimed wherein the second and fifth firmware images are programmed, then the power state transitions occur, then programming the second and fourth firmware images to then proceed to programming the first firmware image. In this manner, the prior art of record, both alone and in combination, fail to teach or render obvious to one of ordinary skill in the art the claimed limitations of updating the first firmware image via the steps as claimed. For these reasons, the claim is determined to be allowable.
Claim 16 recites the following limitations: “program, based at least in part on receiving the command, the second firmware image and the fifth firmware image; transition, by the memory device and based at least in part on programming the second firmware image and the fifth firmware image, from the second power state to the first power state and back to the second power state; program, based at [east in part on transitioning back to the second power state, the third firmware image and the fourth firmware image; and program the first firmware image based at least in part on programming the second firmware image, the third firmware image, the fourth firmware image, and the fifth firmware image.” Claim 16 is determined to be allowable on a similar basis as claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Douglass et al. (US 10,572,166) – Figure 1 and corresponding disclosure wherein maintaining backup copies of firmware for boot is discussed.
Baik et al. (US 2013/0042098) – Figure 15 and corresponding disclosure wherein updating a firmware boot image is discussed.
Hung et al. (US 2015/0193308) – Paragraph [0026] wherein maintaining a plurality of backup boot images is discussed.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/ Supervisory Patent Examiner, Art Unit 2135
Prosecution Insights