DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 19/098,783 filed on 4/2/2025 which is a divisional of application 17/852,059 filed on 6/28/2022, which claim priority to provisional application 63/215,680 filed on 6/28/2021.
Applicant’s election without traverse of claims 3-7 in the reply filed on 6/1/2026 is acknowledged.
Claims 1-2 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/1/2026.
Claims 3-7 have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/2/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the nest loop" in line 3. There is insufficient antecedent basis for this limitation in the claim. Should this instead say, “the nested loop?”
Claims 5-7 are rejected because they depend from a base claim that is currently rejected and fail to cure the deficiencies of the base claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al. (US 2020/0234119) and Madar, III et al. (US 2020/0342350).
With respect to claim 3, Shi teaches of a method for executing loops in a circuit device, the method comprising: storing configuration state data for a plurality of iterations of a first loop (fig. 3, 5; paragraph 18, 42, 59-61; where the devices store the AI models),
wherein the configuration state data for the first loop comprises control data for setting a state of a first control element in a circuit device (paragraph 16-18, 59; where the AI chip is configured using an AI model to perform an AI task);
iterating through the first loop, wherein at each iteration of the first loop a state of the first control element is updated based on the configuration data corresponding to the iteration of the first loop (fig. 3, 5; paragraphs 41-43, 59-62; where at each iteration, the AI model is updated using the previous AI models).
Shi fails to explicitly teach of the configuration state data being stored in a local registry table.
However, Madar teaches of storing parameters for a convolution neural network model in local memory registers (fig. 1; paragraph 67; where CNN parameters are stored in the fastest memory available, which is often local registers).
The combination of Shi and Madar teaches of iterating through the first loop, wherein at each iteration of the first loop a state of the first control element is updated based on the configuration data corresponding to the iteration of the first loop stored in the local registry table (Shi, fig. 3, 5; paragraph 18, 42, 59-61; Madar, fig. 1; paragraph 67; in the combination the AI model/weights are stored in Madar’s local registers).
Shi and Madar are analogous art because they are from the same field of endeavor, as they are directed to managing artificial intelligence/machine learning models.
It would have been obvious to one of ordinary skill in the art having the teachings of Shi and Madar before the time of the effective filing of the claimed invention to store the AI model parameters of Shi in the local registers of Madar. Their motivation would have been to more quickly access the parameters (Madar, paragraph 67).
Claim(s) 4 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi and Madar as applied to claim 3 above, and further in view of Wu et al. (US 2019/0073590).
With respect to claim 4, Shi teaches of wherein the first loop is a first inner loop of a nested loop (fig. 2, 5; paragraph 29, 60-62; where the iterative updating of the AI model (claimed inner loop) is within the iterative process that includes the updating the training configuration parameters (claimed outer loop)) and
wherein the method comprises: storing configuration state data for an iteration of a first outer loop of the nest loop ((fig. 2, 5; paragraph 34, 40, 60-62; where as the training configuration parameters are updated based on their prior values, those values must be stored).
Shi fails to explicitly teach of wherein the method comprises: storing configuration state data for an iteration of a first outer loop of the nest loop in a local memory of the circuit device.
However, Wu teaches of wherein the method comprises: storing configuration state data for an iteration of a first outer loop of the nest loop in a local memory of the circuit device (paragraph 60; where trainers store the parameter data in local memory).
Shi, Madar, and Wu are analogous art because they are from the same field of endeavor, as they are directed to managing artificial intelligence/machine learning models.
It would have been obvious to one of ordinary skill in the art having the teachings of Shi, Madar, and Wu before the time of the effective filing of the claimed invention to store the training parameters of the combination of Shi and Madar in local memory as taught in Wu. Their motivation would have been to more easily access the parameters.
With respect to claim 6, the combination of Shi, Madar, and Wu teaches of retrieving the configuration state data for the iteration of the first outer loop from the local memory after a last iteration of the first inner loop (Shi, fig. 2, 5; paragraph 29, 34, 40, 59-62; where after the max iteration count of updating the AI model is reached, the training configuration parameters are updated. As the training configuration parameters are updated based on their past values, they must be retrieved from their location in Wu’s local memory to be updated).
The reasoning for obviousness is the same as indicated above with respect to claim 4.
With respect to claim 7, the combination of Shi, Madar, and Wu teaches of wherein retrieving the configuration state data for the iteration of the first outer loop comprises storing the configuration state data for the iteration of the first outer loop in the local registry table (Shi, Shi, fig. 2, 5; paragraph 29, 34, 40, 59-62; Madar, paragraph 67; where in the combination, as the training configuration parameters are being updated, it would be beneficial to store them in the registers of Madar to increase the speed at which they can be updated).
Shi, Madar, and Wu are analogous art because they are from the same field of endeavor, as they are directed to managing artificial intelligence/machine learning models.
It would have been obvious to one of ordinary skill in the art having the teachings Shi, Madar, and Wu before the time of the effective filing of the claimed invention to store the training configuration parameters being accessed in the local registers in the combination of Shi, Madar, and Wu as taught in Madar. Their motivation would have been to more quickly access the parameters (Madar, paragraph 67).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi, Madar, and Wu as applied to claim 4 above, and further in view of Catthoor et al. (US 2020/0159809).
With respect to claim 5, the combination of Shi, Madar, and Wu fails to explicitly teach of wherein the configuration state data for the iteration of a first outer loop comprises a configuration state for an address generator, a counter, or a data selector.
However, Catthoor teaches of wherein the configuration state data for the iteration of a first outer loop comprises a configuration state for an address generator, a counter, or a data selector (paragraph 106; where the configuration state of the data selectors/multiplexers is reconfigurable based on the control signals and parameters. In the combination with Shi, Madar, and Wu, this occurs with the updated the training configuration parameters).
Shi, Madar, Wu, and Catthoor are analogous art because they are from the same field of endeavor, as they are directed to managing artificial intelligence/machine learning models.
It would have been obvious to one of ordinary skill in the art having the teachings Shi, Madar, Wu, and Catthoor before the time of the effective filing of the claimed invention to incorporate the configuring the data selectors/multiplexers using the configuration states in the combination of Shi, Madar, and Wu as taught in Catthoor. Their motivation would have been to more efficiently configure the access the parameters.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lovell et al. (US 2022/0413590) discloses a neural network including CNN processors where a controller applies any number of selected configurations or network parameters to a selected circuit configuration to process a subsequent layer of the network according to the selected configuration parameters and selected input data.
Reiher et al. (US 2018/0275758) discloses configurations of the system are updated based on the configuration inputs received. A state of the system is repeatedly computed, whereby each computed state corresponds to a latest updated configuration that was available before starting to compute said each computed state. While repeatedly computing a state of the system, a surrogate function is obtained, upon completion of each computation, which surrogate function approximates a function of said each computed state; and at least one type of feedback is repeatedly provided.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
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