Prosecution Insights
Last updated: October 02, 2026
Application No. 19/099,191

OVERCURRENT PROTECTION CIRCUIT AND METHOD

Non-Final OA §103
Filed
Jan 28, 2025
Priority
Jul 29, 2022 — CN 202210907469.8 +1 more
Examiner
FINCH III, FRED E
Art Unit
Tech Center
Assignee
Dometic Sweden AB
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
741 granted / 924 resolved
+20.2% vs TC avg
Strong +17% interview lift
Without
With
+17.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
27 currently pending
Career history
952
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
47.0%
+7.0% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 924 resolved cases

Office Action

§103
DETAILED ACTION This Office action is in response to the application and preliminary amendment filed on 28 January 2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 4-7, and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP H08251800 A to TOSHIBA CORP (hereinafter “Toshiba”)1. In re claims 1 and 11, Toshiba discloses an overcurrent protection circuit and the corresponding protection method performed by its use (see Figs. 1-2), wherein a power supply (11-13) is connected to a a switch module (23) configured to disconnect the power supply from and connect the power supply to the [load] a sampling module (22, 28) that samples a current flowing through the compressor controller and converts the current into a sampling voltage (Abstract, [0014]-[0015]); a reference module (not shown; providing threshold Vref) that provides a reference voltage (Vref) to set an overcurrent protection threshold ([0014]-[0015]); a determining module (29) that compares the sampling voltage with the reference voltage, wherein when it is determined that the sampling voltage is greater than the reference voltage, a determining signal outputted by the determining module transitions to an overcurrent determining signal ([0014]-[0015]); a determining signal control module (31, 32, 33) that includes a trigger element (31) and a switch element (32), wherein the trigger element receives the overcurrent determining signal (input of 31 from 29) and generates a first trigger signal (output of 31) based on the overcurrent determining signal, and the switch element receives the first trigger signal (input of 32 from 31) and generates an overcurrent shutdown signal (output of 32) based on the first trigger signal, wherein the determining signal control module further comprises a signal control element (33); a switch control module (34, 25-27) that controls, based on the overcurrent shutdown signal (input of 34 from 32), the switch module to disconnect the power supply from the compressor controller ([0014]-[0016]); and a setting module (14) that provides a first setting signal (output of 14 to 33), wherein the signal control element (33) locks the overcurrent shutdown signal based on the first setting signal and the first trigger signal ([0018]-[0019]), such that the power supply is able to be kept disconnected from the [load] id.). Toshiba discloses the claimed invention as explained above except for the load being a compressor controller for a refrigerator. However, the use of overcurrent protection circuits for protecting compressor controllers for refrigerators was known. Moreover, Toshiba’s device is to be found in the same field of endeavor—that of overcurrent protection circuits for machine controllers, in this case being for a turbine generator controller ([0001]-[0002]). As such, Toshiba’s overcurrent protection circuit is clearly capable of the intended use expressed in claim 1. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Toshiba’s overcurrent protection circuit to a compressor controller for a refrigerator in order to obtain the protection benefits taught by Toshiba in that particular application of use. Such implementation would have represented the use of a known device for its intended purpose in an application where such use was conventional and common practice in the art, and thus would not have required the exercise of inventive skill. In re claims 2 and 12, Toshiba as modified discloses wherein when the compressor controller requires to be restarted: the refrigerator is completely powered off and then powered on again; the setting module provides a second setting signal ([0002]-[0003], [0025]); the determining module is able to determine, when the compressor controller is in a shutdown state, that the reference voltage is greater than the sampling voltage, and the determining module outputs an operation determining signal ([0017]-[0018]: it is understood based on the functionality of the circuit that when the power supply current through switch 23 is turned off, the current goes to zero and comparator 29 will thus determine that the sampled current voltage is less than the reference voltage Vref), wherein the signal control element (33) cooperates, based on the second setting signal (output from 14), with the trigger element (31) that receives the operation determining signal, such that the trigger element generates a second trigger signal ([0018], [0019]), the switch element receives the second trigger signal and releases, based on the second trigger signal, the lock on the output of the overcurrent shutdown signal, so as to output an operation conduction signal ([0018]-[0020]: reset signal from 14 releases the RS latch formed by NAND gates 32/33), and the switch control module controls, based on the operation conduction signal, the switch module to connect the power supply to the compressor controller, so as to restore the operation of the compressor controller ([0019], [0020]: the reset signal results in switch 34 turning off, allowing switch 23 to turn back on and restore the power supply current); and after the compressor controller is restarted, the setting module changes to providing a first setting signal ([0018], [0020]: it is understood that upon restoration of the power supply, the reset signal from 14 is removed to allow the normal function of the overcurrent protection circuit once more). In re claim 4, Toshiba as modified discloses wherein the determining signal control module is a gate combination circuit (NAND gates 31-33), wherein the trigger element is a first NAND gate circuit (31), the signal control element is a second NAND gate circuit (32), and the switch element is a third NAND gate circuit (33), wherein a second input terminal of the first NAND gate circuit is connected to an output terminal of the determining module (29) as an input terminal of the determining signal control module, and a first input terminal of the first NAND gate circuit is connected to an output terminal of the second NAND gate circuit (32); a second input terminal of the second NAND gate circuit is connected to an output terminal of the first NAND gate circuit (31), and a first input terminal of the second NAND gate circuit is connected to the setting module (14); and a first input terminal and a second input terminal of the third NAND gate circuit are both connected to the output terminal of the first NAND gate circuit (31), and an output terminal of the third NAND gate circuit is used as an output terminal of the determining signal control module (output to switch 34). In re claim 5, Toshiba as modified discloses wherein the setting module (14) comprises a first voltage dividing resistor and a capacitor that are connected in series (see resistor and capacitor connected before the inverters in circuit 14), wherein one terminal of the first voltage dividing resistor is connected to a positive electrode of the power supply (VDD), one terminal of the capacitor is connected to a negative electrode of the power supply (ground or reference node), and a common connection terminal of the first voltage dividing resistor and the capacitor is connected to the signal control element (via the inverters of circuit 14). In re claim 6, Toshiba as modified discloses the switch module is the reference module comprises a second voltage dividing resistor and a third voltage dividing resistor that are connected in series (see voltage dividing resistors connected to non-inverting input of 28), wherein one terminal of the first voltage dividing resistor is connected to a positive electrode of the power supply, and one terminal of the second voltage dividing resistor is connected to the negative electrode of the power supply (see Figs. 1-2); and the determining module is a comparator circuit (28, 29), wherein a positive input terminal of the comparator circuit is connected to a common connection terminal of the first voltage dividing resistor and the second voltage dividing resistor (through 28), and a negative input terminal of the comparator circuit is connected to a common connection terminal of the Toshiba discloses the claimed invention except for the transistor being an N-MOSFET. However, the use of N-MOSFETs for power switching applications including overcurrent protection devices was well-known and common practice in the art. Further, the selection of a particular type of transistor for such applications was a routine matter for the ordinary artisan. For instance, an N-MOSFET might be selected for its fast switching and low channel resistance properties. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced the BJT switch module transistor with an N-MOSFET to realize well-known advantages such as fast switching and low channel resistance, thus increasing efficiency of the circuit. In re claim 7, Toshiba as modified discloses wherein the switch control module comprises a first NPN transistor (25) and a second NPN transistor (26), wherein a base of the first NPN transistor is connected to an output terminal of the determining signal control module (through 34), a collector of the first NPN transistor is connected to the positive electrode of the power supply via a pull-up resistor (27), and an emitter of the first NPN transistor is connected to the negative electrode of the power supply (through output terminals T1, T2); and a base of the second NPN transistor (26) is connected to the collector of the first NPN transistor (through 23), a collector of the second NPN transistor is connected to the positive electrode of the power supply via a pull-up resistor (through 27), and an emitter of the second NPN transistor is connected to the negative electrode of the power supply (through output terminals T1, T2), wherein the collector of the second NPN transistor is connected to a gate of the switch module (through 25). In re claim 9, Toshiba as modified discloses the switch module is the reference module comprises a second voltage dividing resistor and a third voltage dividing resistor that are connected in series (see voltage dividing resistors connected to non-inverting input of 28), wherein one terminal of the first voltage dividing resistor is connected to a positive electrode of the power supply, and one terminal of the second voltage dividing resistor is connected to the negative electrode of the power supply (see Figs. 1-2); and the determining module is a comparator circuit (28, 29), wherein a positive input terminal of the comparator circuit is connected to a common connection terminal of the first voltage dividing resistor and the second voltage dividing resistor (through 28), and a negative input terminal of the comparator circuit is connected to a common connection terminal of the Toshiba discloses the claimed invention except for the transistor being an P-MOSFET. However, the use of P-MOSFETs for power switching applications including overcurrent protection devices was well-known and common practice in the art. Further, the selection of a particular type of transistor for such applications was a routine matter for the ordinary artisan. For instance, an P-MOSFET might be selected for its fast switching and low channel resistance properties. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced the BJT switch module transistor with an P-MOSFET to realize well-known advantages such as fast switching and low channel resistance, thus increasing efficiency of the circuit. In re claim 10, Toshiba as modified discloses wherein the switch module comprises a first NPN transistor (25), a base of the first NPN transistor is connected to an output terminal of the determining signal control module (through 34), a collector of the first NPN transistor is connected to a gate of the switch module via a current limiting resistor (25), an emitter of the first NPN transistor is connected to a negative electrode of the power supply (through output terminals T1, T2), and the gate of the switch module is connected to the positive electrode of the power supply via a current limiting resistor (25). Allowable Subject Matter Claims 3, 8 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 3, the closest prior art in Toshiba discloses the invention according to claim 1 as explained above, but does not further disclose wherein the overcurrent protection circuit further comprises an automatic restart control module, the automatic restart control module comprises a first port and a second port, and the first port detects output of the switch element, wherein when the first port detects an overcurrent shutdown signal outputted by the switch element and the signal has been outputted for a period of time: the second port of the automatic restart control module is able to provide a restart control signal; the determining module is able to determine, when the compressor controller is in a shutdown state, that the reference voltage is greater than the sampling voltage, and the determining module outputs an operation determining signal, wherein the signal control element cooperates, based on the restart control signal, with the trigger element that receives the operation determining signal, such that the trigger element generates a second trigger signal, the switch element receives the second trigger signal and releases, based on the second trigger signal, the lock on the output of the overcurrent shutdown signal, so as to output an operation conduction signal, and the switch control module controls, based on the operation conduction signal, the switch module to connect the power supply to the compressor controller, so as to restore the operation of the compressor controller; and after the compressor controller is restarted, the second port of the automatic restart control module causes the setting module to continue to provide a first setting signal. For example, Toshiba does not disclose the reset circuit 14 in clouding an automatic restart module detecting an output of the switch element 32, nor performing the other functions recited in the claim. Furthermore, the additional prior art on record does not suggest an obvious modification to Toshiba that would have resulted in the claimed solution. Claim 13 recites substantially similar limitations as claim 3 in the form of a method. As such, claim 13 would be allowable for substantially similar reasons, mutatis mutandis, as explained above. With respect to claim 8, the closest prior art in Toshiba discloses the invention according to claim 6 as explained above, but does not further disclose the switch control module comprises a first NPN transistor and a second PNP transistor, wherein a base of the first NPN transistor is connected to an output terminal of the determining signal control module, a collector of the first NPN transistor is connected to the positive electrode of the power supply via a pull-up resistor, and an emitter of the first NPN transistor is connected to the negative electrode of the power supply; and a base of the second PNP transistor is connected to the collector of the first NPN transistor, an emitter of the second PNP transistor is connected to the positive electrode of the power supply, and a collector of the second PNP transistor is connected to a gate of the switch module via a current limiting resistor. That is, Toshiba only discloses the use of NPN transistors and does not contemplate the use of a PNP and an NPN transistor in the switch control module, much less having the particular configurations as recited in the claim. Furthermore, the additional prior art on record does not suggest an obvious modification to Toshiba that would have resulted in the claimed solution. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0079748 discloses an Over-Current Protection Circuit And Method with latching and resetting functions. US 2016/0329699 discloses an AIR CONDITIONER AND COMPRESSOR PROTECTION CIRCUIT THEREOF having a signal latching module and latching cancel signal function. US 2023/0307902 discloses an Intelligent Semiconductor Switch with prevention of permanent tripping of an overcurrent protective circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRED E FINCH III/Primary Examiner, Art Unit 2838 1 For text citations see the English machine translation of Toshiba provided with this Office action.
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Prosecution Timeline

Jan 28, 2025
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
97%
With Interview (+17.2%)
2y 5m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 924 resolved cases by this examiner. Grant probability derived from career allowance rate.

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