DETAILED ACTION
This office action is in response to the application filed on 1/28/25.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 11, 15 and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Williams (US20070146020) in view of Wang et al. (CN114552956 hereinafter Wang).
Regarding Claim 1, Williams discloses a Direct Current to Direct Current (DC-DC) boost circuit (fig. 5a), comprising: a power Metal- Semiconductor Field-Effect Transistor (104); and a control module circuit (102)electrically connected to a control terminal of the power MESFET and configured to provide a control signal capable of controlling turn-on and turn-off of the power MESFET wherein a voltage value of a high-level signal in the control signal is a maximum rated value of a gate-source voltage of the power MESFET (¶90).
Williams does not disclose a voltage value of a high-level signal in the control signal is 0.5 to 0.8 times a maximum rated value of a gate-source voltage of the power MOSFET.
Wang discloses a MOSFET wherein a voltage value of a high-level signal in the control signal is 0.5 to 0.8 times a maximum rated value of a gate-source voltage of the power MOSFET (as presented in the written opinion of the internation search, (¶ 2-87, and figures 1-6) discloses a driving circuit for a MOSFET, which driving circuit provides a suitable driving voltage for the MOSFET. When an operation voltage range of a gate-source electrode of the MOSFET is -10 V to +25 V, that is, when the maximum voltage of the MOSFET is 25 V, the driving circuit may set switching threshold voltage values to -5 V for turning off and +19 V for turning on, i.e. a voltage value of a high-level signal in a driving signal is set to 0.76 times the maximum gate-source limit voltage value of the MOSFET; and a driver chip used by the driving circuit may provide to the MOSFET a peak source current of 4 A and a peak sink current of 6 A. The driving circuit further comprises a gate resistor; and the driving circuit is arranged on a driving circuit board.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Williams to include a MOSFET with gate control as disclosed in Wang to protect a MOSFET from being damaged by an excessively large gate-source voltage.
Regarding Claim 2, Williams does not disclose the control module circuit is further configured such that when providing a sink current to the control terminal of the power MOSFET, a maximum value of the sink current is not less than 0.5A.
Wang discloses the control module circuit is further configured such that when providing a sink current to the control terminal of the power MOSFET, a maximum value of the sink current is not less than 0.5A (¶ 2-87, and figures 1-6) discloses a driving circuit for a MOSFET, which driving circuit provides a suitable driving voltage for the MOSFET. When an operation voltage range of a gate-source electrode of the MOSFET is -10 V to +25 V, that is, when the maximum voltage of the MOSFET is 25 V, the driving circuit may set switching threshold voltage values to -5 V for turning off and +19 V for turning on, i.e. a voltage value of a high-level signal in a driving signal is set to 0.76 times the maximum gate-source limit voltage value of the MOSFET; and a driver chip used by the driving circuit may provide to the MOSFET a peak source current of 4 A and a peak sink current of 6 A. The driving circuit further comprises a gate resistor; and the driving circuit is arranged on a driving circuit board.).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Williams to include a MOSFET with gate control as disclosed in Wang to protect a MOSFET from being damaged by an excessively large gate-source voltage.
Regarding Claim 11, Williams discloses a voltage regulation circuit (fig. 5a) configured to provide a driving voltage (to 104), wherein the driving voltage is not less than a voltage of the high-level signal in the control signal; and a driver chip configured to output the control signal according to the driving voltage (driving voltage is the provided voltage).
Regarding Claim 15, Williams discloses A driving circuit board comprising a DC to DC boost circuit (fig. 5a), comprising: a power Metal- Semiconductor Field-Effect Transistor (104); and a control module circuit (102) electrically connected to a control terminal of the power MESFET and configured to provide a control signal capable of controlling turn-on and turn-off of the power MESFET wherein a voltage value of a high-level signal in the control signal is a maximum rated value of a gate-source voltage of the power MESFET (¶90).
Williams does not disclose a voltage value of a high-level signal in the control signal is 0.5 to 0.8 times a maximum rated value of a gate-source voltage of the power MOSFET.
Wang discloses a MOSFET wherein a voltage value of a high-level signal in the control signal is 0.5 to 0.8 times a maximum rated value of a gate-source voltage of the power MOSFET (as presented in the written opinion of the internation search, (¶ 2-87, and figures 1-6) discloses a driving circuit for a MOSFET, which driving circuit provides a suitable driving voltage for the MOSFET. When an operation voltage range of a gate-source electrode of the MOSFET is -10 V to +25 V, that is, when the maximum voltage of the MOSFET is 25 V, the driving circuit may set switching threshold voltage values to -5 V for turning off and +19 V for turning on, i.e. a voltage value of a high-level signal in a driving signal is set to 0.76 times the maximum gate-source limit voltage value of the MOSFET; and a driver chip used by the driving circuit may provide to the MOSFET a peak source current of 4 A and a peak sink current of 6 A. The driving circuit further comprises a gate resistor; and the driving circuit is arranged on a driving circuit board.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Williams to include a MOSFET with gate control as disclosed in Wang to protect a MOSFET from being damaged by an excessively large gate-source voltage.
Regarding Claim 20, Williams discloses the control circuit comprises: a voltage regulation circuit configured to provide a driving voltage (to 104), wherein the driving voltage is not less than a voltage of the high-level signal in the control signal; and a driver chip configured to output the control signal according to the driving voltage (driving voltage is the provided voltage).
Allowable Subject Matter
Claims 3-10, 12-14 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art fails to disclose: “...a driver chip configured to provide an initial control signal; a voltage regulation circuit configured to provide a driving voltage, wherein the driving voltage is not less than a voltage of the high-level signal in the control signal; an inverting circuit comprising a second resistor and a second switch, wherein a first terminal of the second resistor is electrically connected to an output terminal of the voltage regulation circuit, a second terminal of the second resistor and a first terminal of the second switch are electrically connected to a first node, and a second terminal of the second switch is configured to apply a ground voltage; a control terminal of the second switch is electrically connected to an output terminal of the driver chip; and the second switch is configured to turn on in response to a high-level signal in the initial control signal and to turn off in response to a low-level signal in the initial control signal; and a driving circuit having a first terminal electrically connected to the output terminal of the voltage regulation circuit, a second terminal configured to apply the ground voltage, a control terminal electrically connected to the first node, and an output terminal electrically connected to the control terminal of the power MOSFET; wherein the driving circuit is configured to establish conduction between the first terminal of the driving circuit and the control terminal of the power MOSFET when a voltage at the first node is low, and to establish conduction between the second terminal of the driving circuit and the control terminal of the power MOSFET when the voltage at the first node is high.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 7, the prior art fails to disclose: “...a voltage regulation circuit configured to provide a driving voltage, wherein the driving voltage is not less than a voltage of the high-level signal in the control signal; a driver chip configured to output an initial control signal according to the driving voltage provided by the voltage regulation circuit; a driving circuit having a first terminal electrically connected to an output terminal of the voltage regulation circuit, a second terminal configured to apply a ground voltage, a control terminal configured to receive the initial control signal, and an output terminal electrically connected to the control terminal of the power MOSFET; wherein the driving circuit is configured to establish electrical conduction between the first terminal of the driving circuit and the power MOSFET in response to a high-level signal in the initial control signal, and to establish electrical conduction between the second terminal of the driving circuit and the power MOSFET in response to a low-level signal in the initial control signal.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 12, the prior art fails to disclose: “...a first terminal of the gate resistor is electrically connected to an output terminal of the control module circuit, and a second terminal of the gate resistor is electrically connected to the control terminal of the power MOSFET; and an anode of the diode is electrically connected to the second terminal of the gate resistor, and a cathode of the diode is electrically connected to the first terminal of the gate resistor.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 16, the prior art fails to disclose: “...an inverting circuit comprising a second resistor and a second switch, wherein a first terminal of the second resistor is electrically connected to an output terminal of the voltage regulation circuit, a second terminal of the second resistor and a first terminal of the second switch are electrically connected to a first node, and a second terminal of the second switch is configured to apply a ground voltage; a control terminal of the second switch is electrically connected to an output terminal of the driver chip; and the second switch is configured to turn on in response to a high-level signal in the initial control signal and to turn off in response to a low-level signal in the initial control signal; and a driving circuit having a first terminal electrically connected to the output terminal of the voltage regulation circuit, a second terminal configured to apply the ground voltage, a control terminal electrically connected to the first node, and an output terminal electrically connected to the control terminal of the power MOSFET; wherein the driving circuit is configured to establish conduction between the first terminal of the driving circuit and the control terminal of the power MOSFET when a voltage at the first node is low, and to establish conduction between the second terminal of the driving circuit and the control terminal of the power MOSFET when the voltage at the first node is high.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 18, the prior art fails to disclose: “...a voltage regulation circuit configured to provide a driving voltage, wherein the driving voltage is not less than a voltage of the high-level signal in the control signal; a driver chip configured to output an initial control signal according to the driving voltage provided by the voltage regulation circuit; a driving circuit having a first terminal electrically connected to an output terminal of the voltage regulation circuit, a second terminal configured to apply a ground voltage, a control terminal configured to receive the initial control signal, and an output terminal electrically connected to the control terminal of the power MOSFET; wherein the driving circuit is configured to establish electrical conduction between the first terminal of the driving circuit and the power MOSFET in response to a high-level signal in the initial control signal, and to establish electrical conduction between the second terminal of the driving circuit and the power MOSFET in response to a low-level signal in the initial control signal.” in combination with the additionally claimed features, as are claimed by the Applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20080290911, Williams; Richard K. discloses a MOSFET gate drive with reduced power loss.
US 20170019096, Vecino Vazquez; Enrique et al. discloses a system and method for a switching transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYLE J MOODY/
Primary Examiner, Art Unit 2838
Prosecution Insights