Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 19-20 are rejected under 35 U.S.C. 102(a1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over US 20200310646 A1 (SONG et al).
With respect to claim 1, SONG teaches system comprising: a set of memory components grouped into a block stripe of a memory sub-system (a memory device including a plurality of memory blocks, manage the memory blocks such that each of the memory blocks belongs to a single-level-cell block group or a multi-level-cell block group) [Fig. 1; Par. 0037-0041]; and a processing device operatively coupled to the set of memory components, the processing device being configured to perform operations (memory device including a plurality of memory blocks, and a host to perform a write operation on the plurality of memory blocks)[Fig. 1; Par. 0039-0040].
SONG fails to specifically teach: determining that a first lifetime program-erase count (PEC) of a first portion of the set of memory components is smaller than a second lifetime PEC of a second portion of the set of memory components (a comparison between a first portion and a second portion of the memory). However, one of ordinary skill in the art would have obviously made the comparison, because SON teaches a selection process a result of check the erase/program pulse count of each of the plurality of memory blocks, i.e. implementing a selection, based on program-erase count (PEC), of either a first group of blocks (first portion of the memory) featuring a SLC mode or a second group of blocks (second portion of the memory) featuring MLC storage mode is the result of a comparison (not specifically disclosed) between a first portion and a second portion of the memory (pulse count management block configured to check the erase/program cycling count of each of the plurality of memory blocks to implement a memory block mode management block configured to manage the plurality of memory blocks such that each of the plurality of memory blocks belongs to the single-level-cell block group or the multi-level-cell block group based on the erase/program pulse count variation of the corresponding memory block) [Fig. 3; Fig. 8, (S900, S910, S920, & S930); Par. 0064-0066; Par. 0143-0145; Par. 0041-0042].
SONG further teaches:
lifetime program erase count (after fabrication, an initial pulse count management block: checks and stores an initial erase/program pulse count of each of the plurality of memory blocks included in the memory device; and after test program operation, checks the number of erase pulses used during the test erase operation of each memory block and stores the checked number) [Par. 00134-0135; Par. 0064-0066];
performing a first memory operation on the first and second portions of the set of memory components in response to a first request associated with the block stripe (manage the plurality of memory blocks such that each of the plurality of memory blocks belong to a single-level-cell memory block group or a multi-level-cell memory block group based on a result of the checking of the wear level of the corresponding memory block) [S820, S830, S840, & S850, Fig. 8; Par. 0143-0145];
erasing the block stripe comprising the first and second portions of the set of memory components after performing the first memory operation (a wear level management block configured to check, during the wear level check operation, a wear level of each of the memory blocks having the free block status based on the erase/program pulse count variation of the corresponding memory block, and manage the memory blocks having the free block status such that each of the memory blocks having the free block status belongs to the single-level-cell block group or the multi-level-cell block group based on a result of the checking) [Par. 0144-0147; Par. 0058-0059]; and
after erasing the block stripe, performing a second memory operation on the second portion of the set of memory components without performing the second memory operation on the first portion of the set of memory components in response to a second request associated with the block stripe (memory block select management block selecting, during a subsequent overall operation, based on the final wear levels of the memory blocks that have been calculated by the pulse count variation management block , e.g., the memory block select management block selects, during a subsequent write operation, a memory block having the lowest wear level among the memory blocks each having a free block status such that a memory block having a comparatively low wear level is preferentially selected so that the write operation is performed on the selected memory block, the memory block group having the free block status ) [Par. 0151-0152; Par. 0063-0066; Par. 0042].
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the instant application, to use SONG’s program/erase block count and compare the program/erase count for two memory pools or groups, in order to selectively perform write/program operation on a selected memory block, the memory block group having the free block status, thereby improving data accuracy of a memory block having a high wear level [Par. 0131].
SONG teaches the selection, based on a result of the checking the number of program erase count, such that the memory device control circuit selects a first memory block belonging to the single-level-cell memory block group among multiple memory blocks when the write operation is a write operation for important data, and selects a second memory block belonging to the multi-level-cell memory block group when the write operation is a write operation for normal data [Par. 0064-066].
With respect to claim 2, SONG teaches system, wherein the first and second memory operations comprise writing respective sets of data to the block stripe (the memory device including a plurality of memory blocks grouped into memory pools, each of the plurality of memory blocks to belong to SLC block pool or MLC/TLC block pool based on wear levels, the SLC programmed to store important data such as system data and the MLC/TLC programmed to store normal data) [Par. 0058; Par. 0047].
With respect to claim 3, SONG teaches system, wherein the operations comprise: accessing configuration data comprising a lifetime PEC of each of the set of memory components (pulse count variation management used for referencing the number of program pulses with a pulse count management block configured to check the erase/program cycling count of each of the plurality of memory blocks) [Par. 0064-066].
With respect to claim 4, SONG teaches system, wherein the first portion of the set of memory components comprises a first memory die, and wherein the second portion of the set of memory components comprises a second memory die (memory device or the memory system embedded in various types of package the memory device including a plurality of memory blocks grouped into memory pools, each of the plurality of memory blocks to belong to SLC block pool or MLC/TLC block pool based on wear levels) [Fig. 1; Par. 0047; Par. 0058].
With respect to claim 5, SONG teaches system, wherein the first portion of the set of memory components comprises a set of planes of a plurality of planes of a first memory die, and wherein the second portion of the set of memory components comprises a second memory die (memory device or the memory system embedded in various types of package the memory device including a plurality of memory blocks grouped into memory pools, each of the plurality of memory blocks to belong to SLC block pool or MLC/TLC block pool based on wear levels) [Fig. 1; Par. 0047; Par. 0058].
With respect to claim 6, SONG teaches system, wherein the set of planes is a first set of planes, and wherein the operations comprise: programming the first set of planes in response to the first request associated with the block stripe without programming a second set of planes of the plurality of planes of the first memory die; and programming the second set of planes in response to the second request associated with the block stripe without programming the first set of planes (based on the final wear levels of the memory blocks that have been calculated by the pulse count variation management block , the memory block selected having the lowest wear level among the memory blocks preferentially selected for write operation where each of the plurality of memory blocks to belong to the SLC block pool or the MLC/TLC block pool based on the wear levels, the SLC programmed to store important data such as system data and the MLC/TLC programmed to store normal data) [Par. 0058; Par. 0151-0152; Par. 0063-0066; Par. 0042].
With respect to claim 19, SONG teaches computerized method (software installed in hardware element (memory) to perform the method controlling the operation of the memory device) [Fig. 8, 9, and 19; Par. 0169-0173] that would have lead one of ordinary skill in the art to come with the claimed invention because:
a) Although, SONG fails to specifically teach: determining that a first lifetime program-erase count (PEC) of a first portion of the set of memory components is smaller than a second lifetime PEC of a second portion of the set of memory components, SONG teaches a selection process being a result of method step check the erase/program pulse count of each of the plurality of memory blocks because (implementing a selection, based on program-erase count (PEC), of either a first group of blocks (first portion of the memory) featuring a SLC mode or a second group of blocks (second portion of the memory) featuring MLC storage mode is the result of a comparison (not specifically disclosed) between a first portion and a second portion of the memory) Par. 0064-0066; Par. 0143-0145; Par. 0041-0042].
b) SONG teaches:
(pulse count management block configured to check the erase/program cycling count of each of the plurality of memory blocks to implement a memory block mode management block configured to manage the plurality of memory blocks such that each of the plurality of memory blocks belongs to the single-level-cell (SLC) block group or the multi-level-cell (MLC) block group based on the erase/program pulse count variation of the corresponding memory block). However, one of ordinary skill in the art would have obviously made the comparison, because [Fig. 3; Fig. 8, (S900, S910, S920, & S930); Par. 0064-0066; Par. 0143-0145; Par. 0041-0042].
performing a first memory operation on the first and second portions of the set of memory components in response to a first request associated with the block stripe (manage the plurality of memory blocks such that each of the plurality of memory blocks belong to a single-level-cell memory block group or a multi-level-cell memory block group based on a result of the checking of the wear level of the corresponding memory block) [S820, S830, S840, & S850, Fig. 8; Par. 0143-0145];
erasing the block stripe comprising the first and second portions of the set of memory components after performing the first memory operation (a wear level management block configured to check, during the wear level check operation, a wear level of each of the memory blocks having the free block status based on the erase/program pulse count variation of the corresponding memory block, and manage the memory blocks having the free block status such that each of the memory blocks having the free block status belongs to the single-level-cell block group or the multi-level-cell block group based on a result of the checking) [Par. 0144-0147; Par. 0058-0059]; and
after erasing the block stripe, performing a second memory operation on the second portion of the set of memory components without performing the second memory operation on the first portion of the set of memory components in response to a second request associated with the block stripe (memory block select management block selecting, during a subsequent overall operation, based on the final wear levels of the memory blocks that have been calculated by the pulse count variation management block , e.g., the memory block select management block selects, during a subsequent write operation, a memory block having the lowest wear level among the memory blocks each having a free block status such that a memory block having a comparatively low wear level is preferentially selected so that the write operation is performed on the selected memory block, the memory block group having the free block status ) [Par. 0151-0152; Par. 0063-0066; Par. 0042].
c) Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the instant application, to use SONG’s program/erase block count and compare the program/erase count for two memory pools or groups, in order to selectively perform write/program operation on a selected memory block, the memory block group having the free block status, thereby improving data accuracy of a memory block having a high wear level [Par. 0131].
With respect to claim 20, SONG teaches non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations (memory system being element of an electronic device such as a computer comprising a controller having a processor, where the controller can be implement as software installed in hardware element (memory) to perform the method controlling the operation of the memory device), addressed in claim 19, above [Par. 0169-0173].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 20200310646 A1 (SONG et al) in view of US 20230251788 (BORDUIA et al).
With respect to claim 7, SONG teaches the invention as claimed, but fails to specifically teach alternating between selecting the first set of planes and selecting the second set of planes for being programmed in response to each subsequent request associated with the block stripe. However, BORDIA teaches data storage device (flash memory device divided into a plurality of dies), where each die of the plurality of dies includes a plurality of physical or logical blocks, the blocks being dynamically arranged into metablocks or block pools [Par. 0006-0008; Par. 0026-0028], where blocks in a control pool are swapped with blocks in a host pool upon exceeding a program-erase count (PEC) threshold [Par. 0037-0039]. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the instant application, to combine SONG’s erase block count for selection of memory block with BORDIA’s swapping the memory block group having the free block status, in order to thereby improve data accuracy of a memory block having a high wear level as the swapping algorithm can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event, as taught by BORDIA [Par. 0021].
Allowable Subject Matter
Claims 8-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150113207 A1 (SHIN) method involving: grouping memory blocks of a nonvolatile memory device based on program counts or erase counts of the respective memory blocks, into a primary group and a secondary group which has program counts or erase counts larger than the primary group; a reprogram operation performed for memory blocks included in the primary group; a read retry operation performed for a selected memory cell of a memory block included in the primary group or the secondary group based on a read retry voltage set for each of the primary group and the secondary group.
WO 2025250699 A1 (STONELAKE et al) teaching processing device to access a plurality of block stripes and to determine a program erase cycle count for each block stripe of the plurality of block stripes, wherein: the processing device may designate a first block stripe of the plurality of block stripes as a cache memory block stripe based on first block stripe having a lower program erase cycle count and may designate a second block stripe of the plurality of block stripes as an FTL block stripe based on the second block stripe having a higher program erase cycle count.
US 20240069730 A1 (YAMPARALA et al) teaching method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block.
US 20200249870 (GOLA et al) teaching memory system includes a controller that assigns a first PEC to a first metablock based on a first number of structures of a memory across which the first metablock is distributed, a controller to assign a second PEC to a second metablock based on a second number of the structures of the memory across which the second metablock is distributed, the controller selecting one of the first metablock or the second metablock to be used based on the first PEC and the second PEC.
US10332604B2 teaching apparatuses, systems, and methods for managing configuration parameter for non-volatile data storage; control module configured to limit erase dwell times for blocks of a non-volatile memory medium to satisfy a threshold; block classification module configured to group blocks of a non-volatile memory medium based on retention times for the blocks; a block access module configured to access at least one group of blocks using a read voltage threshold selected based on a grouping.
US 20240053922 A1 (HE) teaching memory system configured to: receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.
US 20230058038 A1 (ZAINUDDIN et al) teaching apparatuses and techniques for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode, wherein the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold.
US 20210342097 A1 (LIN et al) teaching rewritable non-volatile memory module comprising a plurality of areas, each of the plurality of areas comprising a plurality of physical erasing units, and each of the plurality of physical erasing units having a plurality of memory cells, and the data writing method comprising: receiving a write command from a host system; and determining, according to a write amplification factor (WAF) of a first area.
Salkhordeh, Reza • Mutlu, Onur • Asadi, Hossein, “An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories”, ARXIV.ORG, 2019.
Y. Zhou, F. Wu, W. Huang and C. Xie, "LiveSSD: A Low-Interference RAID Scheme for Hardware Virtualized SSDs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 7, pp. 1354-1366, July 2021.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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