Detailed Action
summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on February 05, 2025.
2. Claims 1-14 are pending and have been examined.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 02/05/2025 and 07/04/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
4. Drawings submitted on 02/05/2025 are acceptable.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is vague and unclear and leaves the reader in doubt. It is unclear how the configuration of the voltage doubler circuit connected to the tap such that the voltage-doubler circuit receives a first voltage from both the first and the second secondary windings and a second voltage from only the second secondary winding”. For the purpose of clarification, applicant should add more claim language to explain/verify in what method is the first and second voltages provide to the specific winding . For the purpose of this examination, examiner understood that when Q2 is controlled OFF and Q1 is controlled ON, Cd2 receives a voltage from the secondary winding connected between SO and S2 and when Q2 is controlled ON and Q1 is controlled OFF, Cd4 receives a voltage from both secondary windings connected between S1 and SO and between SO and S2.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 14 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Unannounced inverter/applicant Korean Gift “CN114389459”. Hereafter, Korean.
In regard to claim 1, Korean disclose a circuit (Fig.7: mode of voltage doubling rectification) comprising: first and second output terminals (Vo+ and Vo-) ; a transformer (Figure 7: transformer 3) including a primary winding and a secondary winding (Np and NS), the secondary winding (NS) includes a tap that divides the secondary winding into first and second secondary windings (between S1&S0 and S0&S2 windings are middle tapped at S0 and equivalent to first and second winding) ; a rectifier circuit (D1 and D2) connected to the secondary winding (D1 and D3 connected to NS) ; and
a voltage-doubler circuit (capacitor Cd1 and Cd4) connected to the tap such that the voltage-doubler circuit (capacitor Cd1 and Cd4) receives a first voltage from both the first and the second secondary windings and a second voltage from only the second secondary winding (Figure 7; when 02 is controlled OFF and 01 is controlled ON, Cd2 receives a voltage from the secondary winding connected between SO and S2 and when 02 is controlled ON and 01 is controlled OFF, Cd4 receives a voltage from both secondary windings
connected between S1 and SO and between SO and S2).
In regard to claim 2, Korean disclose (Fig.7), wherein the voltage-doubler circuit includes first and second capacitors connected in series (Cd2 and Cd4 are in series ) with each other and connected in parallel with the first and second output terminals (Cd2 and Cd4 are configured in parallel to Vout- and Vout+) .
In regard to claim 3, Korean disclose (Fig.7), wherein the first voltage is applied to the first capacitor (voltage applied to across capacitor CD2) and the second voltage is applied to the second capacitor (voltage applied to across capacitor CD4) such that an output voltage across the first and the second output terminals is a sum of the first voltage and the second voltage (it is understood/implicit in the art that the total output voltage of a half-wave or full-wave voltage doubler is equal to the sum of the DC voltages stored across the first and second capacitors connected in series.)
In regard to claim 4, Korean disclose (Fig.7),The circuit of claim 2 or 3, wherein the rectifier circuit includes first and second diodes (D1 and D3 respectively.)
In regard to claim 5, Korean disclose (Fig.7),wherein each of the first and the second capacitors includes first and second ends (Cd2 and Cd4 have a positive and negative plate ); each of the first and the second diodes includes an anode and a cathode (D1 and D3) ; the anode of the first diode is connected to the first end of the first secondary winding (anode of the D1 is connected to the first end of the first secondary winding S0) ; a cathode of the second diode (D3) is connected to the second end of the first secondary winding and to the first end of the second secondary winding (cathode of D3 is connected to S0 through the first winding terminal S1) and ;
the first terminal of the first capacitor is connected to the cathode of the first diode (positive plate of Cd2 is connected to the cathode D1) and to the first output terminal (Vout+);
the second terminal of the first capacitor is connected to the first terminal of the second capacitor (negative plate of Cd2 is connected to the positive plate of Cd4) ;
a node (a connection node between Cd2 and Cd4) defined by a connection between the second terminal of the first capacitor (Cd2) and the first terminal of the second capacitor (cd4) is connected to the second end of the second secondary winding (positive plate of Cd4 is coupled to S2); and
the second terminal of the second capacitor (negative plate of Cd4) is connected to the anode of the second diode (anode of D3) and the second output terminal (Vout-).
In regard to claim 8, Korean disclose (Fig.7),a converter (Fig.7; converting Vin to Vout) comprising: first and second input terminals (Vin+ and Vin- coupled to rectifier 1 and asymmetric half-bridge 2) and an integrated circuit (IC) ( Fig.7: asymmetric half-bridge 2 is integrated in the same package enclosed by the dotted box 2 . Furthermore, it is well known in the art that the half bridge configured in an integrated circuit because it provide massive reductions in size, weight, and cost compared to discrete electronic components) connected to the first and the second input terminals (Vin+ and Vin-) and the primary winding (P1 and P2) .
In regard to claim 14, Korean disclose (Fig.7),wherein during an OFF period of the IC, the first voltage is applied to the first capacitor; and during an ON period of the IC, the second voltage is applied to the second capacitor (the ON/OFF status of switch Q1 and Q2 applied voltage to the first and second capacitor Cd1 and Cd2).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over
Korean Gift “CN114389459” in a view of Wang “20160111965”.
In regard to claim 6, Korean disclose (Fig.7) transformer (3) but fails to teach a substrate; wherein the transformer is embedded in the substrate.
Whereas, Wang disclose transformer (Fig. 5, TX1) having substrate; wherein the transformer is embedded in the substrate (Fig. 2: the embedded magnetic component transformer device includes a first winding in region 310 of the substrate, a second winding in the region 320 of the substrate, and an auxiliary winding in the region 330 of the substrate, see parag.0045 and abstract.
It would have been obvious to one of ordinary skilled person in the art before the effective filing date of the invention to modify the transformer of Korean to include the transformer is embedded in the substrate as taught by Wang because embedded transformer device provides better isolation between input side and output side windings, and allows an oscillating LC circuit to be set up in the case of a short circuit, preventing high power from extending between the input and output terminals and thereby avoiding damage to the connected electrical components, thus it improve the reliability of the circuit., see abstract
In regard to claim 7, Korean as modified disclose (Fig.7), the primary winding and the secondary winding are interleaved (Fig. 7: primary and secondary winding P1 and S1 . Examiner noted that primary winding and the secondary winding are interleaved based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome .
8. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over
Korean Gift “CN114389459” in a view of Choudhary “20170194868”.
In regard to claim 9, Korean disclose (Fig.7) second input terminal (Vin) but fails to disclose a load- compensation circuit connected to the second input terminal.
Whereas, Choudhary disclose the load-compensation circuit (resistor 260
and the operational amplifier 265,Paragraph 15) connected to Vin terminal.
It would have been obvious to one of ordinary skilled person in the art before the effective filing date of the invention to modify the voltage doubling rectification of Korean to include the load compensation resistor 260 and the operational amplifier 265 as taught by Choudhary because it reduces component stress/transient during load fluctuation, thus it improve the reliability of the circuit.
In regard to claim 10, Korean as modified disclose (Fig.7) input terminal (Vin + and Vout).
Furthermore, Choudhary disclosed the load-compensation circuit (resistor 260
and the operational amplifier 265,Paragraph 15) : a resistor connected to the second input terminal (resistor 260 connect to Vin) ; and an operational amplifier (opamp 265) connected across the resistor (260) .
9. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over
Korean Gift “CN114389459” in a view of Enod “JP2001275356”.
In regard to claim 11, Korean as modified disclose (Fig.7) discloses a converter but fails to teach a third output terminal (capacitors 14 and 18 are connected in series at the node and node output terminals is coupled to precipitator electrode unit 3 and on generator 5.
Whereas Enod a power supply unit having a capacitors 14 and 18 are connected in series at the node and node output terminals is coupled to precipitator electrode unit 3 and on generator 5.
It would have been obvious to one of ordinary skilled person in the art before the effective filing date of the invention to modify the voltage doubling rectification of Korean to include third output terminal as taught by Enod because the third terminal serves as the designated point where the processed electrical signal, voltage, or current is delivered power to an external device such as the precipitator electrode unit 3 and on generator 5, thus it improve the reliability of the circuit.
In regard to claim 12, Korean as modified disclose (Fig.7) disclose the converter.
Furthermore, Enod disclose the third output terminal is connected to the capacitors 14 and 18.
In regard to claim 13, Korean as modified disclose (Fig.7) discloses the third output series regulator; wherein the third output terminal is connected to the series regulator (the node between capacitors 14 and 18 is coupled to precipitator electrode unit 3 and on generator 5. Examiner noted that the third output series regulator; wherein the third output terminal is connected to the series regulator is based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome ..
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang “CN223798114” the present invention disclose the utility model claims a voltage doubling and current doubling rectifying circuit of asymmetric half-bridge AC-DC single-stage converter, which is a switching power supply technology, belonging to the technical field of new energy power conversion and power electronics.
Unannounced “CN216699838” the present invention discloses the utility model model claims an asymmetric half-bridge isolation type-stage PFC converter and control circuit thereof, which is a switch power supply technology, belonging to the technical field of power electronics.
Lin “CN112087150” the invention relates to an isolation type boost converter, especially relates to an isolation type boost converter with high boost ratio.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
