DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-14 are objected to because of the following informalities: Claim 1, lines 11-12 recite, “another of the main electrodes”, which should be corrected to “another one of the main electrodes”. Claims 2-12 depend from Claim 1. Claims 13 and 14 have similar recitations and similarly corrected. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "the other main electrode" in line 18. There is insufficient antecedent basis for this limitation in the claim. Claims 2-12 depend from Claim 1, and is rejected due to dependency to a rejected claim. Claims 13, 14 have similar recitations and similarly rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takatani et al. (US 2014/0183609).
Regarding Claim 1, Takatani discloses a semiconductor device (Figures 1-9) comprising:
a multi-gate transistor(100, Figures 1A-1G, corresponding elements in other Figures) including a plurality of field effect transistors each having a pair of main electrodes and a gate electrode disposed between the pair of main electrodes, the field effect transistors being electrically coupled in series while sharing the main electrodes coupled in series (source, drain, gate terminals S1, D1, G1, S2, D2, G2 etc. of each of the FETs in 100 connected in series, Figures 1A-1G);
a first terminal being electrically coupled to one of the main electrodes of the field effect transistor at one end of the series-coupled field effect transistors of the multi-gate transistor, the first terminal receiving or outputting a signal (source S1, Figure 1B, source coupled to RF power/input signal, Figure 8A); and
a second terminal being electrically coupled to another of the main electrodes of the field effect transistor at another end of the series-coupled field effect transistors of the multi-gate transistor, the second terminal receiving supply of a fixed potential (drain D3, Figure 1B, drain coupled to 3V, Figure 8A), wherein the gate electrode of at least one of the field effect transistors of the multi-gate transistor is electrically coupled to the other main electrode of the same field effect transistor (gate terminal coupled to the source terminal of the FETs in 100, Figures 1A-1G).
Regarding Claim 2, Takatani discloses the semiconductor device according to Claim 1, wherein the gate electrode of each of all the field effect transistors of the multi-gate transistor is electrically coupled to the other main electrode of the same field effect transistor (gate terminal coupled to the source terminal of the FETs in 100, Figures 1A-1G).
Regarding Claim 9, Takatani discloses the semiconductor device according to Claim 1, wherein each field effect transistor includes a nitride semiconductor (Paragraph 12, “…said multi-gate E-FET can be a GaN FET”, Paragraph 41, Claim 6).
Regarding Claim 10, Takatani discloses the semiconductor device according to Claim 1, wherein the first terminal receives or outputs a DC signal, and the second terminal receives supply of an operating power supply potential or a reference potential of a high frequency circuit (Figure 8A, Abstract).
Regarding Claim 11, Takatani discloses the semiconductor device according to Claim 10, wherein the high frequency circuit includes a power amplifier (Figures 8A, RF power input, Paragraph 3, application in cell phone).
Regarding Claim 12, Takatani discloses the semiconductor device according to Claim 1, wherein the multi-gate transistor is included in an electrostatic breakdown protection circuit (Abstract, Paragraphs 19-20).
Claim 13 recites a semiconductor module comprising a semiconductor device, the semiconductor device includes a multi-gate transistor including the limitations as recited in Claim 1. Therefore, Claim 13 is rejected similarly to Claim 1 (Takatani discloses an ESD protection device, Abstract, Paragraph 19-20).
Claim 13 recites an electronic apparatus comprising a semiconductor device, the semiconductor device includes a multi-gate transistor including the limitations as recited in Claim 1. Therefore, Claim 14 is rejected similarly to Claim 1 (Takatani. discloses an ESD protection device in cell phone applications).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Takatani et al. (US 2014/0183609).
Regarding Claim 5, Takatani discloses the semiconductor device according to Claim 1, wherein the gate electrode and the other main electrode are coupled via a wiring with a resistance value in the order of 100 Ω (resistance value of 150, 160, 161, Figure 1B, Claim 6).
Takatani does not specifically disclose the wiring with a smaller specific resistance value than a specific resistance value of the same gate electrode and the same main electrode. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select/adjust the resistance value based on the desired protection level and other device parameters for safe and optimal operation.
Regarding Claim 6, Takatani discloses the semiconductor device according to Claim 5, wherein the other main electrode and the wiring are coupled by ohmic junction (resistor 150, 160, 161, Figure 1B).
Regarding Claim 8, Takatani discloses the semiconductor device according to Claim 5, wherein the gate electrode and the other main electrode are coupled at a resistance value (Claim 6). Takatani does not specifically disclose the resistance value being 100 Ω or below. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select/adjust the resistance value based on the desired protection level and other device parameters for safe and optimal operation.
Claims 3-4, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Takatani et al. (US 2014/0183609) in view of Shibasaki et al. (US 5,430,310).
Regarding Claim 3, Takatani discloses the semiconductor device according to claim 1, wherein each field effect transistor includes high electron mobility transistors (HEMT) (Paragraph 41).
Takatani does not specifically disclose that each field effect transistor includes a gate insulating field effect transistor forming the gate electrode with a gate insulating film interposed at a semiconductor layer.
Shibasaki discloses a semiconductor device comprising a field effect transistor and layer structure of the field effect transistor (Figures 8A-8C for example) including a gate insulating field effect transistor forming the gate electrode with a gate insulating film interposed at a semiconductor layer (comprising layer 4 under gate electrode 6 above channel layer 3, Figure 8A, Figures 8B-8C, Column 7, lines 44-62, “a second compound semiconductor layer 4 serving as an insulating barrier layer is not doped with any donor impurity and only the InAs layer serving as the channel layer is doped with the donor impurity…”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the semiconductor device of Takatani, a gate insulating field effect transistor as taught by Shibasaki, to function as an insulating barrier layer between the gate electrode and the channel layer.
Regarding Claim 4, combination of Takatani and Shibasaki discloses the semiconductor device according to Claim 3, wherein the gate insulating film has a film thickness of 20 nm or more in terms of conversion into an oxide film thickness (Column 15, lines 3-8, “… The thickness of the second compound semiconductor layer 4 suitably ranges from 50 to 1,000 .ANG.. More specifically, the thickness thereof should fall within such a range as no conduction electron is present in the second compound semiconductor layer 4 after the formation of gate electrode 6”).
Regarding Claim 7, Takatani discloses the semiconductor device according to claim 5, wherein each field effect transistor includes high electron mobility transistors (HEMT) (Paragraph 41).
Takatani does not specifically disclose that the other main electrode of each field effect transistor includes an ohmic electrode disposed at a channel layer of the same field effect transistor, and the ohmic electrode is disposed at the channel layer, has a same conductive type as a carrier flowing to the same channel layer, and is electrically coupled to the channel layer via a high purity density region having higher impurity density than the channel layer.
Shibasaki discloses a semiconductor device comprising a field effect transistor and layer structure of the field effect transistor (Figures 8A-8C for example), wherein the field effect transistor comprising a first and second main electrodes and a gate electrode (7, 5, 6 respectively, Figures 8A-8C), the main electrodes of the field effect transistor includes an ohmic electrode disposed at a channel layer of the field effect transistor, and the ohmic electrode is disposed at the channel layer, has a same conductive type as a carrier flowing to the same channel layer, and is electrically coupled to the channel layer via a high purity density region having higher impurity density than the channel layer (Column 7, lines 44-62, “a second compound semiconductor layer 4 serving as an insulating barrier layer is not doped with any donor impurity and only the InAs layer serving as the channel layer is doped with the donor impurity…”, Column 22, lines 5-9, “…the patterns of the source electrode 5 and the drain electrode 7 comprising three layers 51, 52 and 53, and 71, 72 and 73 were formed by the lift-off technique to obtain ohmic junctions between these electrodes and the InAs layer 3….”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the semiconductor device of Takatani, main electrode layer structure as taught by Shibasaki, to function as an insulating barrier layer between the respective layers to provide safe and fast operation to provide the desired ESD protection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 2018/0350707, IDS Document) discloses a semiconductor device in Figure 1, comprising:
a multi-gate transistor including a plurality of field effect transistors each having a pair of main electrodes and a gate electrode disposed between the pair of main electrodes, the field effect transistors being electrically coupled in series while sharing the main electrodes GP1 to GP5 coupled in series, each having a gate drain and source electrodes);
a first terminal being electrically coupled to one of the main electrodes of the field effect transistor at one end of the series-coupled field effect transistors of the multi-gate transistor, the first terminal receiving or outputting a signal (source/drain terminal coupled to pad 110); and
a second terminal being electrically coupled to another of the main electrodes of the field effect transistor at another end of the series-coupled field effect transistors of the multi-gate transistor, the second terminal receiving supply of a fixed potential (drain/source terminal coupled to VSS), wherein the gate electrode of at least one of the field effect transistors of the multi-gate transistor is electrically coupled to the other main electrode of the same field effect transistor (Figure 1, GP1 to GP5 with gate terminal coupled to the source/drain terminal);
Langguth et al. (US 2021/0242677) discloses and ESD protection device 102, 102b, 102d in Figures 2A, 2B including plurality of diode connected transistors 126 coupled between a pad TN and supply voltage terminal VDD;
Takatani et al. (US 2014/0183544) discloses multi-gate ESD protection device (Figure 7D for example) including plurality of diode connected transistors coupled between a first terminal and supply second terminal;
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/LUCY M THOMAS/Examiner, Art Unit 2838, 8/08/2026
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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