Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This application is in response to the application filed on February 10, 2025.
2. Claims 1-12 are pending and have been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 02/10/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 02/10/2025 are acceptable.
Specification
6. i) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
ii) Abstract exceeds 150 words. Appropriate action is required.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 and 9-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “ the same current-output ration” in line 9. There is insufficient antecedent basis for this claim limitation.
Claims 3-4 and 9-12 dependent on claim 2, thus are also rejected because of their dependency.
Allowable Subject Matter
8. Claims 1 and 5-8 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 is allowed because the prior art in the record fails to disclose or suggest a zero crossing detection circuit including the limitation of “the detection module configured to produce, when a voltage at the detection point rises to a predetermined voltage, a falling edge for triggering a zero-crossing, wherein an absolute difference between the predetermined voltage and 0 V does not exceed 100 mV, the short pulse generation module configured to output, when receiving the falling edge, a high-level pulse signal with a predetermined pulse width, the output signal processing module configured to perform an operation based on an operating-state signal indicating an operating state of the upper transistor, an output signal of the detection module and an output signal of the short pulse generation module; and when it is determined from the operating-state signal that the upper transistor is in an off state, and when receiving the high-level pulse signal, the output signal processing module configured to output a control signal for turning off the lower transistor.”
Claims 5-8 are dependent on claim 1, thus are also allowed because of their dependency.
Conclusion
In regard to claim 1, NI “CN 112816767” is considered to be the closest prior art.
NI discloses disclose (description, paragraphs 0006-0065, and figures 1-2) that: provided is a BUCK-type DC-DC power supply chip; a power transistor is a P-type MOS transistor; a free-wheeling transistor is an N-type MOS transistor; and an intersection point where the power transistor is connected to the free-wheeling transistor and an inductor is an SW point. Provided is an inductor current zero-crossing detection circuit, comprising: an input module, configured to monitor a voltage of the SW point, add a lead threshold to the voltage of the SW point, and simultaneously collect the voltage of the SW point and power ground potential to output same to a comparison module; a comparison module, configured to compare the voltage of the SW point with the power
ground potential voltage, both of which are collected by the input module, and output a comparison result indicating whether zero-crossing occurs to the inductor current to an output module; and an output module, configured to shape a signal outputted by the comparison module and then output same. The range of the lead threshold is 0.46 to 0.5, i.e., an early flipping occurring when the SW voltage ranges from -0.5 mv to -0.46
mv. When the power transistor is turned off, the zero-crossing detection circuit monitors the voltage of an SW end. When the power transistor operates normally, a current value flowing through the SW end increases from negative to positive to 11 *R4, and the output of the entire circuit changes from low to high, i.e., zero-crossing occurring to the inductor current, the free-wheeling transistor is controlled to be turned off by means of a logic circuit. When the output module outputs a high level signal, since the output module comprises seven inverters,the comparison module outputs a low level signal.
However, NI fails to discloses or suggest “a zero-crossing detection circuit further comprises: a narrow-pulse-width generation module, configured to output a high level pulse signal having a preset pulse width when receiving a zero-crossing trigger falling edge; and an output signal processing module, configured to perform an operation on the basis of the outputted signal of the narrow-pulse-width generation module.”
Xu “CN1207722054” The invention relates to the technical field of electronics, specifically to an over-current zero-point detection circuit and a PFC circuit system.
AN ”CN121441052” The invention relates to the technical field of power supply management, specifically to a zero-crossing detection circuit, a controller and a DC-DC converter.
BI “20200144901” The present invention generally relates to voltage converters and, more particularly, to zero-current detectors (ZCDs) for synchronous buck converters.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
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