Prosecution Insights
Last updated: August 06, 2026
Application No. 19/103,269

MAGNETIC SENSOR DEVICE

Non-Final OA §102§103
Filed
Feb 12, 2025
Priority
Sep 02, 2022 — JP 2022-139958 +1 more
Examiner
MAHONEY, CHRISTOPHER E
Art Unit
Tech Center
Assignee
Aichi Steel Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
903 granted / 1086 resolved
+23.1% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
26 currently pending
Career history
1102
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
42.0%
+2.0% vs TC avg
§102
33.4%
-6.6% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1086 resolved cases

Office Action

§102 §103
DETAILED ACTION Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Umehara (JP2001-318131). Umehara teaches a magnetic sensor device (see fig. 8, par. 43) comprising: a wiring board (30); a plurality of magnetic detection elements (15A) mounted on the wiring board; and an integrated circuit (18) mounted on the wiring board and electrically connected to the magnetic detection elements, the integrated circuit having a rectangular shape (see 18 in fig. 8), wherein the plurality of magnetic detection elements is disposed outside the integrated circuit when viewed in a direction normal to the wiring board (see 15A in fig. 8), and the magnetic detection elements whose magnetism sensing directions are parallel to each other (see the elongation direction of the two MI elements 15A in fig. 8) are disposed at least at positions along two edges of the integrated circuit, the two edges being opposite each other (see fig. 8). Regarding claim 2, the plurality of magnetic detection elements 15A each has an elongated shape, and a longitudinal direction of each magnetic detection element is parallel to an edge of the integrated circuit on an adjacent side. See fig. 8. Regarding claim 6, the plurality of magnetic detection elements is a magneto-impedance element. See ¶43. Claim(s) 1-3, 6 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato (U.S. Publication No. 20040104724). Sato teaches a magnetic sensor device 10 comprising: a wiring board 10a; a plurality of magnetic detection elements (Gr1, Gr2) mounted on the wiring board; and an integrated circuit 31 mounted on the wiring board and electrically connected to the magnetic detection elements, the integrated circuit having a rectangular shape (fig. 1), wherein the plurality of magnetic detection elements is disposed outside the integrated circuit when viewed in a direction normal to the wiring board (see fig. 1), and the magnetic detection elements whose magnetism sensing directions are parallel to each other are disposed at least at positions along two edges of the integrated circuit, the two edges being opposite each other (see fig. 1). Regarding claim 2, fig. 1 depicts that the plurality of magnetic detection elements each has an elongated shape, and a longitudinal direction of each magnetic detection element is parallel to an edge of the integrated circuit on an adjacent side. Regarding claims 3 and 14, fig. 1 shows four or more of the magnetic detection elements (Gr1-Gr4), wherein the magnetic detection elements are disposed at positions respectively along four edges of the integrated circuit when viewed in a direction normal to the wiring board. Regarding claim 6, GMRs are a magneto-impedance element. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4-5 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Umehara (JP2001-318131) in view of Lynde (U.S. Publication No. 20170030981). Umehara teaches the salient features of the claimed invention except for a relay pad constituting part of an electrical path between the integrated circuit and the magnetic detection elements and a connection wiring electrically connecting the relay pad and the integrated circuit are formed, each magnetic detection element is connected to the relay pad with a bonding wire, and the bonding wire is disposed at a position where the bonding wire does not overlap the integrated circuit when viewed in a direction normal to the wiring board. Lynde teaches in fig. 2 that it was known to provide a relay pad constituting part of an electrical path between the integrated circuit and the magnetic detection elements and a connection wiring electrically connecting the relay pad and the integrated circuit are formed, each magnetic detection element is connected to the relay pad with a bonding wire, and the bonding wire is disposed at a position where the bonding wire does not overlap the integrated circuit when viewed in a direction normal to the wiring board. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the features of Lynde for the purpose of allowing use of unpackaged magnetometers. Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (U.S. Publication No. 20040104724) in view of Yamamoto (U.S. Publication No. 2020/0319270). Sato teaches the salient features of the claimed invention except for a relay pad constituting part of an electrical path between the integrated circuit and the magnetic detection elements and a connection wiring electrically connecting the relay pad and the integrated circuit are formed, each magnetic detection element is connected to the relay pad with a bonding wire, and the bonding wire is disposed at a position where the bonding wire does not overlap the integrated circuit when viewed in a direction normal to the wiring board. Yamamoto teaches in figs. 1-4 that it was known to provide a relay pad constituting part of an electrical path between the integrated circuit and the magnetic detection elements and a connection wiring electrically connecting the relay pad and the integrated circuit are formed, each magnetic detection element is connected to the relay pad with a bonding wire, and the bonding wire is disposed at a position where the bonding wire does not overlap the integrated circuit when viewed in a direction normal to the wiring board. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the features of Yamamoto for the purpose of allowing use of unpackaged magnetometers. Claim(s) 7, 9-10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (U.S. Publication No. 20040104724) in view of Yamamoto (U.S. Publication No. 2020/0319270). Sato teaches an analog circuit and ADC. Sato teaches the salient features of the claimed invention except for explicitly disclosing the integrated circuit includes a plurality of analog circuit units connected to the plurality of magnetic detection elements, respectively, each of the analog circuit units includes at least a current application circuit configured to apply a current to a corresponding magnetic detection element, a sample hold circuit to which an output signal of the corresponding magnetic detection element is input, and an AD conversion circuit configured to convert an analog signal temporarily stored in the sample hold circuit into a digital signal, and the analog circuit unit and the corresponding magnetic detection element connected to each other are adjacent to each other with each edge of the integrated circuit interposed therebetween. ¶4 of Yamamoto teaches a current application circuit configured to apply a current to a corresponding magnetic detection element. ¶55 teaches a sample-hold circuit (not shown) for holding the output voltage of the detection coil for a predetermined period, an A/D converter for converting the output voltage thus held into a digital value. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the features of Yamamoto for the purpose of enabling the sensor to function and provide data. Regarding claim 9, Sato teaches the plurality of magnetic detection elements each has an elongated shape, a longitudinal direction of each magnetic detection element is parallel to an edge of the integrated circuit on an adjacent side., the analog circuit unit has an elongated shape, and a longitudinal direction of the analog circuit unit is parallel to an edge of the integrated circuit on an adjacent side. See fig. 1. Regarding claim 10, Sato teaches four or more of the magnetic detection elements, wherein the magnetic detection elements are disposed at positions respectively along four edges of the integrated circuit when viewed in a direction normal to the wiring board. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the four or more for the purpose of four or more of the analog circuit units, and the analog circuit units are disposed at positions respectively along four edges of the integrated circuit when viewed in the direction normal to the wiring board for the purpose of enabling each sensor. The applicant should note that it has been held that mere duplication of the essential working parts of a device involve only routine skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Regarding claim 13, ¶55 of Yamamoto teaches the current application circuit is configured to apply a pulse current or a high-frequency current to the corresponding magnetic detection element. Claim(s) 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (U.S. Publication No. 20040104724) in view of Yamamoto (U.S. Publication No. 2020/0319270) and further in view of Itabuchi (TW202413986). Sato as modified teaches the salient features of the claimed invention except for an output circuit configured to output a signal from the integrated circuit to an outside is disposed between the plurality of analog circuit units when viewed in a direction normal to the wiring board. Itabuchi teaches an output circuit 26 configured to output a signal S27 to an outside. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the features of Itabuchi for the purpose of providing output of measurments. Regarding claim 11 it would have been obvious to one of ordinary skill in the art at the time the invention was filed to dispose the output circuit between the plurality of analog circuit units disposed at positions along two edges of the integrated circuit for the purpose of proximity to connected parts. The applicant should note that it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (U.S. Publication No. 20040104724) in view of Yamamoto (U.S. Publication No. 2020/0319270) Itabuchi (TW202413986) and further in view of Ausserlechner (U.S. Publication No. 20110234215). Sato as modified teaches the salient features of the claimed invention except for the integrated circuit is flip-chip mounted on the wiring board. Ausserlechner teaches that it was known to flip-chip mount a sensor on the board. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the features of Ausserlechner for the purpose of utilizing fast manufacturing methods. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Theuss (U.S. Publication No. 20080135959) teaches flip chip mounting. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E MAHONEY whose telephone number is (571)272-2122. The examiner can normally be reached 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephanie Bloss can be reached at 571-272-3555. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER E MAHONEY/Primary Examiner, Art Unit 2852
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Prosecution Timeline

Feb 12, 2025
Application Filed
Jul 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
95%
With Interview (+11.6%)
1y 11m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1086 resolved cases by this examiner. Grant probability derived from career allowance rate.

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