Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7 and 19 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Rezzi [7888973].
As to claim 1,
Strap [7888973] teaches an integrated circuit with a clock distribution network for a computational node array, comprising:
a node array comprising a plurality of nodes, the plurality of nodes comprising a first node and a second node that abuts the first node [col. 11, line 10-13“The matrix memory 950 may be described as a set of comparators that can store the result of a comparison. For example, matrix memory 950 may include multiple comparators, latches, flip-flops, and the like.”- matrix is formed of array],
wherein the first node comprises clock distribution circuitry configured [ summary: col. 1: line 48-52: “time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements, and multiple comparators, which are fewer in number than the total number of delay elements. The multiple comparator 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals. ”-receiving and passing the refence and clock is equivalent to clock distributor] to:
receive a clock signal, provide the clock signal to computing circuitry of the first node [ col. 3, line 36-38: “The ADPLL 100 can generate an oscillatory output signal, denoted OUTPUT, at a desired frequency in response to a reference signal from an external source (not shown).”], and
provide the clock signal to the second node, wherein the clock signal is delayed by a unit of delay in the second node relative to the first node [ col 5, line 35-40: The second TDC 207 can receive the reference signal and the divided feedback signal, OUT.sub.DIV, which may also be described as a clock signal, from the feedback divider 225. The second TDC 207 and can generate a phase transient signal, .PHI..sub.ERR.sub.-- ” and col. 8, line 56-58: “TDC comparison matrices in FIGS. 6A-C, one can refer to Table 1 below. Table 1 shows, in normalized delay units, an example of the sampling instants of a reference signal due to the combination of delays from the two delay lines in a 20-state TDC. In this example, when the reference signal is delayed by more than the number of units in a given entry of the delay matrix in Table 1, the time difference between the reference signal and the clock signal may be represented by a ONE in a corresponding entry in the TDC comparison matrix of FIGS. 6A-C. The number of delay units can range from zero up to one less than the number of quantization intervals in TDC. Table 2 shows an example of the sampling instants for a 15-state TDC. ”- it can be delaying unit].
As to claim 2,
Rezzi teaches the first node is configured to: receive the clock signal from two upstream nodes and provide the clock signal to two downstream nodes with the unit of delay [summary: time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements, and multiple comparators, which are fewer in number than the total number of delay elements. The multiple comparator 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals.”]
As to claim 7,
Rezzi teaches the node array comprises a plurality of compute nodes and a plurality of globals nodes [summary: “he multiple comparator 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals.”]
As to claim 19,
Rezzi teaches this claim according to the reasoning set forth in claim 1 supra. Furthermore, teaches providing the clock signal to a neighboring node of the node array [ summary: “time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements”- passes to another element, which is neighboring element ]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rezzi [7888973], in view of Forbes [20070046385]
As to claim 10,
Rezzi teaches array but does not explicitly teach node array has a strapped H-tree clock distribution topology.
However Forbes [20070046385] teaches node array has a strapped H-tree clock distribution topology.[0051: “a clock system with a time delay oscillator, in which the clock distribution includes taps along the transmission line. Since the input impedance to CMOS transistors is high, they present only a small capacitive load. Thus, as shown in FIG. 14, the low impedance transmission line can be tapped at various locations as the line runs around an integrated circuit. This will provide timing signals with a well-controlled frequency at remote locations on an integrated circuit and can be used as a clock distribution system rather than a conventional clock tree or "H" tree distribution system ”]
It would have been obvious to person of ordinary skill in the art before the effective filing date of the claimed invention to combine teaching of Rezzi and Forbes because both are directed toward clock distribution. Furthermore, Forbes improves upon Rezzi by being able to distribute clock in H-tree distribution such that it can efficiently provide clock to each geometric symmetry.
Allowable Subject Matter
Claim 4-6, 8-9, 20 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11-18 allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET).
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/KESHAB R PANDEY/ Primary Examiner, Art Unit 2176
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