Prosecution Insights
Last updated: October 23, 2026
Application No. 19/103,545

CIRCUIT CONTROL METHOD AND UNIT, AND APPARATUS

Non-Final OA §102
Filed
Feb 12, 2025
Priority
Aug 12, 2022 — CN 202210968509.X +1 more
Examiner
MOODY, KYLE J
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ace Power And Technology Co. Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
522 granted / 576 resolved
+22.6% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
7 currently pending
Career history
589
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
32.7%
-7.3% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
27.1%
-12.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 576 resolved cases

Office Action

§102
DETAILED ACTION This office action is in response to the application filed on 2/12/25. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Inventorship This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a). Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3, 4 and 6-9 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Oswald et al. (US20090066301, hereinafter Oswald). Regarding Claim 1, Oswald discloses (fig. 2) a circuit control method which is applied to a power source apparatus, the power source apparatus comprising a switching boost circuit (L, SW3) that comprises at least one power semiconductor device, and the circuit control method comprising: collecting an input signal (via 10) and an output signal (r1/r2, Vsense) of the switching boost circuit; determining, according to the input signal, the output signal, and circuit information of the switching boost circuit, a control scheme with a highest electrical energy conversion efficiency as a target control scheme from a plurality of control schemes to be selected, wherein the control schemes to be selected comprise a control scheme corresponding to each of a plurality of working modes of the switching boost circuit for the at least one power semiconductor device; and controlling conduction and shutdown of the at least one power semiconductor device according to the target control scheme (¶50-56). Regarding Claim 3, Oswald discloses the plurality of working modes comprise a discontinuous mode and/or a continuous mode; the control schemes to be selected comprise a control scheme corresponding to each of the working modes among the discontinuous mode and/or the continuous mode of the switching boost circuit for the at least one power semiconductor device; the control scheme corresponding to the continuous mode for the at least one power semiconductor device comprises a continuous conduction mode control scheme; the control scheme corresponding to the discontinuous mode for the at least one power semiconductor device comprises an N-th valley discontinuous conduction mode control scheme, where N comprises at least one positive integer greater than or equal to 1 (¶50-56). Regarding Claim 4, Oswald discloses (fig. 2) when the power of the switching boost circuit is greater than or equal to a first preset power, the plurality of control schemes to be selected comprise the continuous conduction mode control scheme and the N-th valley discontinuous conduction mode control scheme (¶50-56). Regarding Claim 6, Oswald discloses (fig. 2) an input signal and an output signal of the switching boost circuit comprises: collecting an input signal and an output signal of the switching boost circuit at an interval of one or more preset control cycles (¶32, cycles based on operating frequency). Regarding Claim 7, Oswald discloses (fig. 2) pre-forming corresponding relationships between different input signals and output signals and the plurality of control schemes (32, 54). Regarding Claim 8, Oswald discloses (fig. 2) a circuit control unit which is applied to a power source apparatus, the power source apparatus comprising a switching boost circuit (L, SW3) that comprises at least one power semiconductor device (SW3), the circuit control unit comprising: a signal collection module configured to collect an input signal (via 10) and an output signal (r1/r2, Vsense) of the switching boost circuit; a control adjustment module configured to determine, according to the input signal, the output signal, and circuit information of the switching boost circuit, a control scheme with a highest electrical energy conversion efficiency as a target control scheme from a plurality of control schemes to be selected, wherein the control schemes to be selected include a control scheme corresponding to each of a plurality of working modes of the switching boost circuit for the at least one power semiconductor device; and a switching control module configured to control conduction and shutdown of the at least one power semiconductor device according to the target control scheme (¶50-56). Regarding Claim 9, Oswald discloses a power source apparatus, comprising a switching boost circuit and the circuit control unit according to claim 8. (fig. 2) Allowable Subject Matter Claims 2 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, the prior art fails to disclose: “...the determining, according to the input signal, the output signal, and circuit information of the switching boost circuit, a control scheme with a highest electrical energy conversion efficiency as a target control scheme from a plurality of control schemes to be selected comprises: calculating, according to the input signal, the output signal and the circuit information of the switching boost circuit, circuit losses of the switching boost circuit under the plurality of control schemes to be selected, wherein the circuit losses comprise an inductor core loss, an inductor winding loss, a switching transistor turn-on loss, a switching transistor turn-off loss, a switching transistor on-state loss, a rectifier diode on- state loss and a rectifier diode switching loss; determining the electrical energy conversion efficiency of each of the control schemes to be selected according to the circuit loss and the output signal thereof; and determining a control scheme with a highest electrical energy conversion efficiency as a target control scheme from the plurality of control schemes to be selected. .” in combination with the additionally claimed features, as are claimed by the Applicant. Regarding claim 5, the prior art fails to disclose: “..when the power of the switching boost circuit is less than or equal to a second preset power, the plurality of control schemes to be selected comprise an M-th valley discontinuous conduction mode control scheme, wherein the second preset power is less than the first preset power, and M comprises at least one positive integer greater than or equal to a preset value” in combination with the additionally claimed features, as are claimed by the Applicant. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20070115248, Roberts; John K. et al. discloses solid state lighting panels with variable voltage boost current sources. US 20090256535, Houston; Michael J. et al. discloses a varying operation of a voltage regulator, and components thereof, based upon load conditions. US 20100327838, Melanson; John L. discloses a switching power converter with current sensing transformer auxiliary power supply. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYLE J MOODY/ Primary Examiner, Art Unit 2838
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Prosecution Timeline

Feb 12, 2025
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
98%
With Interview (+7.7%)
2y 0m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 576 resolved cases by this examiner. Grant probability derived from career allowance rate.

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