The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: NONVOLATILE SRAM WITH RESISTIVE STORAGE AND SELECTIVE STORE AND RESTORE PATHS.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Taniguchi (US PGPUB # 20170221563) in view of Roehr (US PGPUB # 20060181916).
With respect to independent claims 1 Taniguchi/Roehr discloses: A storage device [Taniguchi fig 1] comprising:
a volatile storage unit including a volatile storage node that complementarily holds data [SRAM 2 – Taniguchi 0014, 0019, 0035-0036 and fig 1], and an access transistor connected between the volatile storage node and a bit line [SRAM comprises a first access transistor and a second access transistor. One end of the first access transistor is connected to a gate of the second load transistor, a gate of the second drive transistor, and the first storage node. Another end of the first access transistor is connected to a first bit line. A gate of the first access transistor is connected a word line. One end of the second access transistor is connected to a gate of the first load transistor, a gate of the first drive transistor, and the second storage node. Another end of the second access transistor is connected to the second bit line. A gate of the first second transistor is connected the word line – Taniguchi 0018, 0108, fig 1 ]; and
a nonvolatile storage unit including a nonvolatile storage node that complementarily holds the data [non-volatile SRAM memory cell 1 of the present invention comprises an SRAM 2, a plurality of non-volatile memory sections 4a, 4b, and 4c, and a node controller 5 – Taniguchi 0036, 0038-0040, 0087, fig 1],
a first switch connected between the nonvolatile storage node and a store line [each of the first ReRAM (RT1, RT2, RT3) connected in series to the first switch transistor (ST1, ST2, ST3) and the second ReRAM (RB1, RB2, RB3) connected in series to the second switch transistor (SB1, SB2, SB3) … other end of the first ReRAM RT1 and the other end of the second ReRAM RB1 are connected to the common memory source line … one end of the first ReRAM (RT2, RT3) in the first memory cell (M2a, M3a) is connected to one end of the second ReRAM (RB2, RB3) in the second memory cell (M2b, M3b). The other end of the first ReRAM (RT2, RT3) and the other end of the second ReRAM (RB2, RB3) are connected to the common memory source line (MS2, MS3) – Taniguchi 0039-0041, 0079-0083, fig 1], and
a second switch connected between the nonvolatile storage node and the volatile storage node [a plurality of switch transistors establish SRAM/ReRAM connection - Taniguchi 0039-0041, 0079-0083, fig 1 in view of Roehr 0026-0027, 0030-0032, fig 1].
Taniguchi does not explicitly teach two different switches, one connected between the nonvolatile storage node and a store line, and the other connected between the nonvolatile storage node and the volatile storage node. Nevertheless, in the same field of endeavor Roehr a hybrid volatile/non-volatile memory cell having a volatile latch formed by cross coupled first and second inverters (Roehr 0015-0016), at least two resistive memory elements retaining complementary conductance states (Roehr 0026-0029), and further teaching teaches two resistive memory elements are provided for non-volatile storage of a data item, with a first resistive memory element 4 being coupled via a read unit 6 to the input of the first inverter 2, and a second resistive memory element 5 being coupled via the read unit 6 to the input of the second inverter 3. The read unit 6 has a first switching transistor 7 in order to couple the first memory element 4 to the input of the first inverter 2, and a second switching transistor 8 in order to couple the second memory element 5 to the input of the second inverter 3. The two switching transistors 7, 8 are activated and deactivated via a control signal SET, which is produced by a control unit 9. The control unit is used to send the stored data item to the integrated circuit by writing the content of the data item to be stored as a conductance state in the memory elements to the memory unit 1 – Roehr 0026-0027, 0030-0032, 0035, fig 1. As such, the combination of Taniguchi/Roehr teaches all limitations of the instant claim.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide Taniguchi’s ReRAM cell with Roehr’s separate programming and read/restore paths in the invention of Taniguchi as taught by Roehr because it would be advantageous to permit independent controller backup programming and restore, and to isolate the ReRAM during normal SRAM operations so as to reduce current flow and optimize power consumption (Roehr 0009, 0011) .
With respect to dependent claim 2, Taniguchi/Roehr discloses wherein the first switch includes a store transistor that stores data held in the volatile storage node into the nonvolatile storage node via the store line [data transfer from volatile storage via switch transistor to program ReRAM - Taniguchi 0080-0083, 0087, fig 6; transistor to store line - Roehr 0035-0036, fig 4], and the second switch includes a restore transistor that restores data held in the nonvolatile storage node into the volatile storage node [during SRAM write/restore sb1 connects rb1 to snb and SRAM latch develops complementary state, in other words, ReRAM to SRAM restore – Taniguchi 0054-0063, fig 3 in view of Roehr 0030-0032].
With respect to dependent claim 3, Taniguchi/Roehr discloses wherein the volatile storage unit includes a static random access memory (SRAM), and the nonvolatile storage unit includes a resistive random access memory [Taniguchi 0035-0039].
With respect to dependent claim 4, Taniguchi/Roehr discloses wherein the volatile storage unit includes a flip-flop having the volatile storage node [Taniguchi 0003-0005, 0107-0108; Roehr 0026], the nonvolatile storage unit includes a variable resistance element whose resistance changes on a basis of voltage application [Taniguchi 0039; Roehr 0028], and one end of the store transistor and one end of the restore transistor are connected to one end of the variable resistance element [Taniguchi 0039; Roehr 0035].
With respect to dependent claim 5, Taniguchi/Roehr discloses wherein the flip-flop includes a pair of inverters whose outputs are connected to each other's input [Taniguchi 0003-0005, 0107-0108; Roehr 0026], a connecting point between the outputs and the inputs of the pair of inverters is used as the volatile storage node [Taniguchi 0003-0005, 0107-0108; Roehr 0026], and a connecting point among the variable resistance element, the store transistor, and the restore transistor is used as the nonvolatile storage node [Taniguchi 0039; Roehr 0035-0036].
With respect to dependent claim 6, Taniguchi/Roehr discloses wherein the data held in the volatile storage node is stored into the nonvolatile storage node sequentially via the store line and the store transistor [PROG0 and PROG1 are distinct signals that are understood to be sequential at least some of the time - Taniguchi 0079-0087; Roehr 0035-0036, fig 4]
With respect to dependent claim 7, Taniguchi/Roehr discloses wherein the data held in the nonvolatile storage node is restored into the volatile storage node via the restore transistor [Taniguchi 0057, 0059, 0061-0062; Roehr 0027, 0030-0032, fig 1].
With respect to dependent claim 8 Taniguchi/Roehr discloses a word line that opens and closes the access transistor; a restore select line that opens and closes the restore transistor; a store select line that opens and closes the store transistor; and a nonvolatile (NV) control line connected to the variable resistance element [Taniguchi 0018, 0041, 0055, 0057, 0068, 0070, 0108, fig 1; Roehr 0026, 0030-0032].
With respect to dependent claim 9 Taniguchi/Roehr discloses a sense amplifier that detects data read from the volatile storage unit; and an NV control unit that controls a potential of the store line and a potential of the NV control line on a basis of the data detected by the sense amplifier, and stores the data held in the volatile storage node into the nonvolatile storage node via the store transistor [Taniguchi 0018, 0041, 0055, 0057, 0068, 0070, 0108, fig 1; Roehr 0026, 0030-0032].
With respect to dependent claim 10 Taniguchi/Roehr discloses wherein when the data held in the volatile storage node is stored into the nonvolatile storage node, the NV control unit complementarily sets the potential of the store line depending on the data detected by the sense amplifier, and causes the potential of the NV control line to transition between a high level and a low level [Taniguchi 0018, 0041, 0055, 0057, 0068, 0070, 0108, fig 1; Roehr 0026, 0030-0032].
With respect to dependent claim 11, Taniguchi/Roehr discloses wherein the NV control unit drives the nonvolatile storage unit on a basis of a higher voltage than a drive voltage of the volatile storage unit [Taniguchi 0037, 0079, 0093-0096, fig 8].
With respect to dependent claim 12, Taniguchi/Roehr discloses a power gating transistor that performs power gating of the inverter [Taniguchi 0037, fig 1].
With respect to dependent claim 13, Taniguchi/Roehr discloses wherein a drive force of the store transistor is greater than a drive force of a transistor to be used in the inverter, a drive force of the access transistor, and a drive force of the restore transistor [Taniguchi 0037, 0079, 0093-0096, fig 8].
With respect to dependent claim 14, Taniguchi/Roehr discloses memory cells in which the volatile storage unit and the nonvolatile storage unit are provided, wherein the memory cells are arranged in a row direction and a column direction in a matrix [Taniguchi 0035, 0049, 0116-0117, fig 2].
With respect to dependent claim 15, Taniguchi/Roehr discloses wherein each of the word line, the restore select line, and the store select line extends in the row direction, and each of the bit line, the store line, and the NV control line extends in the column direction [Taniguchi 0049-0050, 0065, fig 1-2].
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Taniguchi/Roehr further in view of Kolar (US PGPUB # 20160078926 ).
With respect to dependent claim 16-17, Taniguchi/Roehr discloses does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Kolar teaches a dual/two-port static random access memory such that the combination of Taniguchi/Roehr/Kolar teaches wherein the volatile storage unit includes a dual/two port SRAM (Kolar title, 0002, fig 2-3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a dual/two-port static random access memory in the invention of Taniguchi/Roehr as taught by Kolar because it would be advantageous and desirable for improving the yield and reliability of memory arrays (Kolar 0003)
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Taniguchi/Roehr further in view of Yuh (US PGPUB # 20210201998 ).
With respect to dependent claim 18, Taniguchi/Roehr discloses does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Yuh teaches a non-volatile static random access memory such that the combination of Taniguchi/Roehr/Yuh teaches a peripheral restore circuit that reads data held in the nonvolatile storage node to the outside of the volatile storage unit [I/O block 30 and controller 40 are outside of memory array 20, the I/O circuit can sense/compare BL and BLB; MRAM retains states and later write them to SRAM, and MRAM to SRAM transfer/restore on power up – Yuh 0026-0028,0035, 0037, 0043-0046, fig 1]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a dual/two-port static random access memory in the invention of Taniguchi/Roehr as taught by Kolar because it would be advantageous for providing the benefits of both SRAM and MRAM memory technology to optimize speed and data retention characteristics of both memories in a hybrid memory system (Yuh 0058)
With respect to dependent claim 19 Taniguchi/Roehr discloses wherein the data held in the nonvolatile storage node is restored into the peripheral restore circuit sequentially via the store transistor and the store line [writing data from the first and second storage node of the SRAM cell to the respective first and second MTJ elements includes sequentially writing the data from the first and second storage node of the SRAM cell to the respective first and second MTJ elements – Yuh 0041, claim 19].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dimmler US Patent # 4809225 teaches: A memory cell includes an SRAM flip-flop cell having two nodes coupled to ferroelectric capacitors so that when the SRAM is powered down, the ferroelectric devices store data and upon power up, transfer the stored data to the SRAM cell. The ferroelectric devices can be bypassed during normal SRAM operations to reduce hysteresis fatigue.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-530p M-R.
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/Marwan Ayash/Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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