DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites a gate voltage Vg using mathematical expression. However, it is not clear what the elements Vs, |Vtd|, Vg(t), Vg(0), t and “delta t” recited in the mathematical expression represent and therefore makes the claim indefinite for failing to particularly point out and not distinctly claiming the subject matter.
Claims 10-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the current saturation drain voltage" in line 13-14. There is insufficient antecedent basis for this limitation in the claim. However, it is noted that claim 10, line 10 recites the “a current saturation source voltage” in line 10, not drain. The Examiner assumed for rejection of the claim that the limitation should have been --a current saturation drain voltage-- in line 10 as best understood that similarly claimed in claim 1.
Claim 11 recites the limitation "the current saturation drain voltage" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the current saturation drain voltage" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claims 13-14 are rejected as being depending upon the rejected base claim 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 8-10, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al (US 2021/0407437 A1).
Claim 1, Jang (Fig. 1-11) discloses a display device (100; Fig. 1; Paragraph [0044]) comprising:
a display panel (110; Fig. 1) including a plurality of pixel rows (SP; Fig. 1; Paragraph [0044]; wherein discloses “a plurality of subpixels SP are aligned in rows and columns”);
a scan driver (120; Fig. 1; wherein discloses a gate driver) configured to provide a scan signal (SCAN; Fig. 6) and a sensing signal (SENSE; Fig. 6) to each of the plurality of pixel rows (Paragraph [0012]; wherein discloses “the scan signal SCAN and the sense signal SENSE may be applied with a high level through the gate line GL”; SP; Fig. 1; Paragraph [0044]; wherein discloses “a plurality of subpixels SP are aligned in rows and columns”);
a data driver (130; Fig. 1) connected to the plurality of pixel rows (SP; Fig. 1; Paragraph [0044]; wherein discloses “a plurality of subpixels SP are aligned in rows and columns”) through a plurality of data lines (DL; Fig. 1; Paragraph [0035]);
a sensing circuit (134; Fig. 4; Paragraph [0099]) connected to the plurality of pixel rows (SP; Fig. 1; Paragraph [0044]; wherein discloses “a plurality of subpixels SP are aligned in rows and columns”) via a plurality of sensing lines (RVL; Fig. 4); and
a controller (140; Fig. 1 and 11) configured to control (Paragraph [0056]) the scan driver (120; Fig. 1), the data driver (130; Fig. 1), and the sensing circuit (134; Fig. 11), and to select at least one pixel row (Paragraph [0084]; wherein discloses sensing from a single gate line) from among the plurality of pixel rows (SP; Fig. 1; Paragraph [0044]; wherein discloses “a plurality of subpixels SP are aligned in rows and columns”) during a vertical blanking period (Blank; Fig. 9) of each frame interval (Frame1; Fig. 9 and [0135-0136]),
wherein the vertical blanking period (Blank; Fig. 9) includes a sensing period (Tracking1 and Tracking2; Fig. 9) during which the sensing circuit (134; Fig. 4) performs a sensing operation (Vsen; Fig. 4) on the selected pixel row (Paragraph [0135-0136]; wherein discloses sensing from a single gate line),
wherein the sensing circuit (134; Fig. 4) is configured to measure a first drain voltage (N2 during Tracking1 of Figure 9; Paragraph [0015]; wherein discloses “a sensing transistor electrically connected between either a source node or a drain node of the driving transistor and a reference voltage line”; N2; Fig. 4) of a driving transistor (DRT; Fig. 4) of each pixel (SP; Fig. 4 and 1) in the selected pixel row (Paragraph [0084]; wherein discloses sensing from a single gate line) at a first point in time (Tracking1; Fig. 9) during the sensing period (Tracking1 and Tracking2; Fig. 9), and to measure a second drain voltage (N2 during Tracking2 of Figure 9; Paragraph [0015]; wherein discloses “a sensing transistor electrically connected between either a source node or a drain node of the driving transistor and a reference voltage line”; N2; Fig. 4) of the driving transistor (DRT; Fig. 4) at a second point in time (Tracking2; Fig. 9) during the sensing period (Tracking1 and Tracking2; Fig. 9), and
wherein the controller (140; Fig. 11) is configured to predict (146; Fig. 11; Paragraph [0141]; Fig. 8) a current saturation (Paragraph [0120]; wherein discloses a saturation state) drain voltage (N2; Fig. 4) of the driving transistor (DRT; Fig. 4) based on the first drain voltage (N2 during Tracking1; Fig. 9) and the second drain voltage (N2 during Tracking2; Fig. 9), and to calculate a threshold voltage variation (Paragraph [0144]; Paragraph [0157-0158]) of the driving transistor (DRT; Fig. 4) based on the difference between (Paragraph [0178]; wherein discloses “ by comparing the reference threshold voltage or the reference mobility stored in the outer memory 180 with it”) a previous saturation drain voltage (180; Fig. 11) and the current saturation drain voltage (148; Fig. 11).
Claim 10, Jang (Fig. 1-11) discloses a threshold voltage sensing method (Fig. 9; wherein figure shows a sensing method) in a display device (100; Fig. 1) comprising a plurality of pixel rows (SP; Fig. 1; Paragraph [0044]; wherein discloses “a plurality of subpixels SP are aligned in rows and columns”), the method (Fig. 9) comprising:
selecting at least one pixel row (Paragraph [0084]; wherein discloses sensing from a single gate line) from among the plurality of pixel rows (SP; Fig. 1; Paragraph [0044]; wherein discloses “a plurality of subpixels SP are aligned in rows and columns”) during a vertical blanking period (Blank; Fig. 9) of each frame interval (Frame1 and Frame2; Fig. 9);
measuring (134; Fig. 4) a first drain voltage (N2 during Tracking1 of Figure 9; Paragraph [0015]; wherein discloses “a sensing transistor electrically connected between either a source node or a drain node of the driving transistor and a reference voltage line”; N2; Fig. 4) of a driving transistor (DRT; Fig. 4) of each pixel (SP; Fig. 4 and 1) in the selected pixel row (Paragraph [0084]; wherein discloses sensing from a single gate line) at a first point in time (Tracking1; Fig. 9) during the sensing period (Tracking1 and Tracking2; Fig. 9) within the vertical blanking period (Blank; Fig. 9);
measuring (134; Fig. 4) a second drain voltage (N2 during Tracking2 of Figure 9; Paragraph [0015]; wherein discloses “a sensing transistor electrically connected between either a source node or a drain node of the driving transistor and a reference voltage line”; N2; Fig. 4) of the driving transistor (DRT; Fig. 4) at a second point in time (Tracking2; Fig. 9) during the sensing period (Tracking1 and Tracking2; Fig. 9);
predicting (146; Fig. 11; Paragraph [0141]; Fig. 8) a current saturation source voltage (Paragraph [0120]; wherein discloses a saturation state) of the driving transistor (DRT; Fig. 4) based on the first drain voltage (N2 during Tracking1; Fig. 9) and the second drain voltage (N2 during Tracking2; Fig. 9); and
calculating a threshold voltage variation (Paragraph [0144]; Paragraph [0157-0158]) of the driving transistor (DRT; Fig. 4) based on the difference between (Paragraph [0178]; wherein discloses “ by comparing the reference threshold voltage or the reference mobility stored in the outer memory 180 with it”) a previous saturation drain voltage (180; Fig. 11) and the current saturation drain voltage (148; Fig. 11).
Claim 2, Jang (Fig. 1-11) discloses wherein the threshold voltage variation (Paragraph [0178]) of the driving transistor (DRT; Fig. 4) is calculated by reflecting the current saturation drain voltage (Fig. 7; Paragraph [0139]; N2; Fig. 9) obtained through the current sensing operation (Paragraph [0142]; Fig. 9) from the previous drain-source voltage obtained through the previous sensing operation (180; Fig. 11).
Claim 4, Jang (Fig. 1-11) discloses wherein the controller (140; Fig. 1) is configured to sequentially select (Paragraph [0050]; wherein discloses sequentially supplying scan signal; Fig. 5; wherein the disclosed embodiment uses the same scan signal for scan and sense signal) the plurality of pixel rows (SP; Fig. 1) in which the sensing operation (Tracking; Fig. 10) is to be performed across a plurality of frame intervals (Frame1 and Frame2; Fig. 10).
Claim 8, Jang (Fig. 1-11) discloses wherein the data driver (130; Fig. 1) is configured to apply a sensing data voltage (Vdata_sen; Fig. 6) to the plurality of data lines (DL; Fig. 1) during the sensing period (Fig. 6; wherein figure shows method of driving during sensing operation),
the scan driver (120; Fig. 1) is configured to apply the scan signal (Scan; Fig. 6) and the sensing signal (Sense; Fig. 6) to the selected pixel row (Paragraph [0084]; wherein discloses sensing from a single gate line) during the sensing period (Fig. 6; wherein figure shows method of driving during sensing operation), and
the sensing circuit (134; Fig. 4) is configured to apply a reference voltage (Vref; Fig. 5) to the plurality of sensing lines (RVL; Fig. 3) before the sensing period (Initial period; Fig. 6), to sample the voltage (Sampling; Fig. 6) of each of the plurality of sensing lines (RVL; Fig. 4) at a first point in time (Tracking1; Fig. 9) during the sensing period (Fig. 9) to measure the first drain voltage (N2; Fig. 4; Paragraph [0078]; wherein discloses Node N2 may be a drain node), and to sample the voltage (Sampling; Fig. 6) of each of the plurality of sensing lines (RVL; Fig. 4) at a second point in time (Tracking2; Fig. 9) during the sensing period (Fig. 9) to measure the second drain voltage (N2; Fig. 4; Paragraph [0078]; wherein discloses Node N2 may be a drain node).
Claim 9, Jang (Fig. 1-11) discloses wherein the vertical blanking period (Blank; Fig. 9) is configured to perform external compensation (Paragraph [0179]; Fig. 11; wherein calculated compensation is external from the display device) for one or more of the lines (Paragraph [0084]; wherein discloses sensing from a single gate line) in each frame (Frame1; Fig. 9).
Claim 12, Jang (Fig. 1-11) discloses wherein the step of calculating the threshold voltage variation (Paragraph [0020]) of the driving transistor (DRT; Fig. 4) includes:
calculating the threshold voltage variation (Paragraph [0178]) of the driving transistor (DRT; Fig. 4) by reflecting the current saturation drain voltage (Fig. 7; Paragraph [0139]; N2; Fig. 9) obtained through the current sensing operation (Paragraph [0142]; Fig. 9) from the previous drain-source voltage obtained through the previous sensing operation (180; Fig. 11).
Claim 13, Jang (Fig. 1-11) discloses wherein the step of selecting the pixel row (Paragraph [0084]; wherein discloses sensing from a single gate line) includes:
sequentially selecting (Paragraph [0050]; wherein discloses sequentially supplying scan signal; Fig. 5; wherein the disclosed embodiment uses the same scan signal for scan and sense signal) the plurality of pixel rows (SP; Fig. 1) in which the sensing operation (Tracking; Fig. 10) is to be performed across a plurality of frame intervals (Frame1 and Frame2; Fig. 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0407437 A1) in view of Lim et al (US 2018/0182283 A1).
Claim 3, Jang (Fig. 1-11) discloses wherein each pixel (SP; Fig. 1 and 3) comprises:
the driving transistor (DRT; Fig. 3) having a gate (Fig. 3; wherein figure shows gate electrode connected to node N1), a source (Paragraph [0078]; wherein discloses node N3 as a source node) receiving a first power voltage (EVDD; Fig. 3), and a drain (Paragraph [0078]; wherein discloses node N2 as a drain node);
a first switching transistor (SWT; Fig. 3) having a gate (Paragraph [0080]) configured to receive the scan signal (SCAN; Fig. 4), a drain (Fig. 3; wherein figure shows electrode of switch SWT connected to the data line DL) connected to a corresponding one of the plurality of data lines (DL; Fig. 3), and a source (Fig. 3; wherein figure shows other electrode of switch SWT connected to node N1) connected to the gate of the driving transistor (DRT; Fig. 3);
a fourth switching transistor (SENT; Fig. 3) having a gate (Paragraph [0081]) configured to receive the sensing signal (SENSE; Fig. 3), a drain (Fig. 3; wherein figure shows electrode of switch SENT connected to node N2) connected to the drain of the driving transistor (DRT; Fig. 3), and a source (Fig. 3; wherein figure shows other electrode of switch SENT connected to line RVL) connected to a corresponding one of the plurality of sensing lines (RVL; Fig. 3); and
a light emitting element (OLED; Fig. 3) having an anode and a cathode connected (Paragraph [0087]; wherein discloses anode and cathode of OLED) between the source (N2; Fig. 3) of the driving transistor (DRT; Fig. 3) and a second power voltage (EVSS; Fig. 3).
Jang does not expressly disclose a storage capacitor having a first electrode connected to the source of the driving transistor, and a second electrode connected to the drain of the driving transistor through a second transistor and to the gate of the driving transistor.
Lim (Fig. 1-8) discloses a storage capacitor (Cst; Fig. 2) having a first electrode connected to the source (Paragraph [0083]; wherein discloses “a source electrode thereof is electrically connected to the Node-C”) of the driving transistor (264; Fig. 2), and a second electrode connected to the drain (Paragraph [0083]; wherein discloses “a drain electrode thereof is electrically connected to the Node-D”) of the driving transistor (264; Fig. 2) through a second transistor (262; Fig. 2) and to the gate (Node A; Fig. 2) of the driving transistor (264; Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jang’s display device by applying a pixel circuit, as taught by Lim, so to use a display device with a pixel circuit for providing an electroluminescence display device capable of compensating various deviations of sub-pixels including both an N-type transistor and a P-type transistor (Paragraph [0019]).
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0407437 A1) in view of Kim et al (US 2018/0130423 A1).
Claim 5, Jang discloses the display device according to claim 1.
Jang does not expressly disclose wherein the controller is configured to randomly select the plurality of pixel rows in which the sensing operation is to be performed across a plurality of frame intervals.
Kim (Fig. 1-22) discloses wherein the controller (21; Fig. 1) is configured to randomly select (Paragraph [0106]) the plurality of pixel rows (Lb, Lc, and La; Fig. 13) in which the sensing operation (Sensing; Fig. 13) is to be performed across a plurality of frame intervals (F(n)-F(n+2); Fig. 13).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jang’s display device by applying randomly sensing target pixels, as taught by Kim, so to use a display device with randomly sensing target pixels for providing to minimize or prevent the sensing
target display line from being recognized as a line dim (Paragraph [0106]).
Claim 14, Jang discloses the threshold voltage sensing method of a display device according to claim 10.
Jang does not expressly disclose wherein the step of selecting the pixel row includes:
randomly selecting the pixel row in which the sensing operation is to be performed from among the plurality of pixel rows in each frame interval.
Kim (Fig. 1-22) discloses wherein the step of selecting the pixel row (Sensing; Fig. 3) includes:
randomly selecting (Paragraph [0106]) the pixel row (Lb, Lc, and La; Fig. 13) in which the sensing operation (Sensing; Fig. 13) is to be performed from among the plurality of pixel rows L1-Ln; Fig. 13) in each frame interval (F(n)-F(n+2); Fig. 13).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jang’s display device by applying randomly sensing target pixels, as taught by Kim, so to use a display device with randomly sensing target pixels for providing to minimize or prevent the sensing
target display line from being recognized as a line dim (Paragraph [0106]).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0407437 A1) in view of Yin et al (US 2021/0335234 A1).
Claim 6, Jang discloses the display device according to claim 1.
Jang does not expressly disclose wherein the source voltage of the driving transistor is fixed to a first power voltage during the sensing period, and the drain voltage of the driving transistor is the same as the gate voltage.
Yin (Fig. 1-6) discloses wherein the source voltage (B; Fig. 1; Paragraph [0040]; wherein discloses source electrode of driving transistor T1 is coupled to the fist power supply line ELVDD) of the driving transistor (T1; Fig. 1) is fixed to a first power voltage (ELVDD; Fig. 1) during the sensing period (Paragraph [0051]; wherein discloses during sensing period first power supply is supplied with a fixed voltage), and the drain voltage (C; Fig. 1; Paragraph [0040]) of the driving transistor (T1; Fig. 1) is the same as the gate voltage (A; Fig. 1; Paragraph [0040]; Fig. 3; wherein during resetting period applying a Vini voltage to both nodes A and C).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jang’s display device by applying a sensing driving method, as taught by Yin, so to use a display device with a sensing driving method for provides an improved display-driving circuit with threshold
voltage compensation and reduction of signal line layout for the OLED display panel (Paragraph [0003]).
Claim 7, Jang discloses the display device according to claim 1.
Jang does not expressly disclose wherein the driving transistor has its gate node and drain node connected when charging the sensing line.
Yin (Fig. 1-6) discloses wherein the driving transistor (T1; Fig. 3) has its gate node (A; Fig. 3) and drain node (C; Fig. 3) connected (Fig. 3; wherein T2 is enabled from signal Sn) when charging (Fig. 3; wherein during resetting) the sensing line (Vsens; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jang’s display device by applying a sensing driving method, as taught by Yin, so to use a display device with a sensing driving method for provides an improved display-driving circuit with threshold
voltage compensation and reduction of signal line layout for the OLED display panel (Paragraph [0003]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0407437 A1) in view of Park et al (KR 10-2017-0036569 A).
Claim 11, Jang discloses the threshold voltage sensing method of a display device according to claim 10.
Jang does not expressly disclose wherein the step of predicting the current saturation drain voltage of the driving transistor includes:
calculating a gate voltage using the mathematical expression
PNG
media_image1.png
79
581
media_image1.png
Greyscale
Park (Fig. 1-13) discloses wherein the step of predicting (Fig. 8, 10, and 11) the current saturation drain voltage (N1; Fig. 3) of the driving transistor (DRT; Fig. 3) includes:
calculating a gate voltage using the mathematical expression (Fig. 20; wherein discloses multiple expressions to calculate the gate voltage Vg).
PNG
media_image1.png
79
581
media_image1.png
Greyscale
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jang’s threshold voltage sensing method by applying a mathematical expression for gate voltage, as taught by Park, so to use a threshold voltage sensing method with a mathematical expression for gate voltage for drastically shortened through two sensing methods during sensing operation of characteristic values or characteristic values for each circuit element in each sub-pixel (See Page 18 of translation).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Adam J Snyder/ Primary Examiner, Art Unit 2623 12/08/2025