DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement filed on February 13, 2025 is considered.
Response to Preliminary Amendment
The preliminary amendment filed on February 13, 2025 is entered, and claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 19 and 20, the claim recites, in relevant part, “selecting an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition, a first of the plurality of error handling modes corresponding to storing a first set of debugging information associated with the memory sub-system, and a second of the plurality of error handling modes corresponding to storing a second set of debugging information associated with the memory sub-system without interrupting a host, the second set being a subset of the first set of debugging information.” This language is indefinite because it is unclear how the “critical event trigger data corresponds to” such condition, and what specific relationship exists between the selecting step and the recited error handling modes. In addition, the phrase “without interrupting a host” is unclear as to whether it is merely a result of the second mode, a functional limitation of the second mode, or a required operational condition of the claimed system. Further, the phrase “the second set being a subset of the first set of debugging information” is unclear because the claim does not distinctly identify the contents of either set or explain how the subset relationship is determined. Accordingly, the metes and bounds of the claim are not reasonably clear to one of ordinary skill in the art.
Claims 2-18 are also rejected because of depending on claim 1, either directly or indirectly, containing the same deficiency.
The following art rejection is based on the best understanding in accordance with 112(b) as stated above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Moran (US 6,615,374 B1) in view of Pandey et al. (US 10,908,987 B1, hereinafter Pandey).
Regarding claim 1, Moran discloses a system as shown in figure 1 comprising: a memory sub-system comprising a set of memory components (figure 1, 152-154 and col. 2 lines 20-30, main memory 150 for one embodiment comprises two memory subsystems 152 and 154. Each memory subsystem 152, and 154 may comprise any suitable memory); and a processing device (figure 1, 102), operatively coupled to the set of memory components and configured to perform operations comprising: receiving critical event trigger data (figure 2, 202 and col. 3 lines 10-15, an error condition associated with the functioning of an integrated circuit device is detected); determining whether the critical event trigger data corresponds to a fatal condition (col. 3 lines 15-16 and col. 4 lines 12-20, whether the detected error condition is a first detected error condition is determined, and error conditions may be categorized as non-fatal and fatal); and selecting an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition, a first of the plurality of error handling modes corresponding to storing a first set of debugging information associated with the memory sub-system (col. 3 lines 46-58 and col. 4 lines 1-11, whether the detected error condition is a first detected error condition is determined for step 204 by determining whether any error conditions have been recorded in the first error status register, if not, the detected error condition is identified as the first detected error condition, wherein the error recordation circuitry may also comprise one or more log registers or other suitable memory device(s) for recording, for step 208, state information associated with the first detected error condition). Moran differs from the claimed invention in not specifically teaching a second of the plurality of error handling modes corresponding to storing a second set of debugging information associated with the memory sub-system without interrupting a host, the second set being a subset of the first set of debugging information. However, Pandey teaches an error handling technique for a computing device includes detecting a memory error during execution of the program instructions to generate a computational result, and execution of the program instructions or program code can be allowed to continue until the current program completes and the computation result is generated by suppressing an interrupt associated with the individual memory error to prevent execution of the program instructions or program code from halting due to the memory error (figure 6, 610 and col. 15 lines 27-34) in order to prevent a system from halting due to a memory error. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moran in having a second of the plurality of error handling modes corresponding to storing a second set of debugging information associated with the memory sub-system without interrupting a host, the second set being a subset of the first set of debugging information, as per teaching of Pandey, in order to prevent a system from halting due to a memory error.
Regarding claim 2 Moran discloses that the first set of debugging information includes a state of the memory sub-system representing a status of at least one of one or more data structures, one or more queues, or one or more state machines (col. 3 lines 28-45, first and next error identification may be performed using suitable error recordation circuitry comprising a first error status register and a next error status register; the first error status register comprises a predetermined number of bits, each representing a respective error condition; and the next error status register comprises a predetermined number of bits, each representing a respective error condition).
Regarding claim 3, Moran discloses that the critical event trigger data includes at least one of Non-Volatile Memory Express (NVMe) command timeout being triggered, Cyclic Redundancy Code (CRC) Errors exceeding a CRC threshold, PCIe AXI Error event, Uncorrectable Errors (IE) event, read or write completion latency exceeding a read or write threshold, reset event information, or memory parity errors exceeding a parity threshold (col. 1 lines 13-27, exemplary error conditions include hardware failures, parity errors, single-bit and multiple-bit error correcting code (ECC) errors, communication protocol violations, etc.).
Regarding claim 4, Moran discloses that the operations comprise: selecting the first of the plurality of error handling modes in response to determining that the critical event trigger data corresponds to the fatal condition; and transmitting an interrupt signal to the host to initiate debugging operations in response to selecting the first of the plurality of error handling modes (col. 4 lines 26-44, an integrated circuit device may encounter a recoverable and continuable error condition, such as data with a single-bit error correcting code (ECC) error for example, followed by a next error condition while servicing the recoverable error condition, and the recoverable error condition may be recorded in the first error status register to trigger an interrupt for servicing the error condition by correcting the data).
Regarding claim 9, Moran teaches that the operations comprise: resetting the memory sub-system; saving the first or second sets of debugging information on the set of memory components; and in response to determining that the first of the plurality of error handling modes has been selected, restricting a set of operations of the memory sub-system to operations performed in a basic function mode (col. 3 lines 10-27, first detected error condition means the first detected error condition since some prior event, such as a device or system reset or a clearing of prior identified error conditions for example, the detected error condition is identified as a first detected error condition if the detected error condition is the first detected error condition, and state information associated with the identified first detected error condition may also be recorded).
Regarding claim 10, Moran discloses that the operations comprise: reserving a first portion of the set of memory components for storing one or more instances of the first set of debugging information; and reserving a second portion of the set of memory components for storing one or more instances of the second set of debugging information (col. 3 lines 28-45 and col. 4 lines 1-11, error recordation circuitry comprising a first error status register and a next error status register, the first error status register comprises a predetermined number of bits, each representing a respective error condition, and the next error status register comprises a predetermined number of bits, each representing a respective error condition, wherein error recordation circuitry may also comprise one or more log registers for recording state information associated with the first detected error condition associated with the first detected error condition for error handling, diagnostics, or debugging).
Regarding claim 19, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 20, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Moran (US 6,615,374 B1) in view of Pandey et al. (US 10,908,987 B1, hereinafter Pandey) as applied to claim 1 above, and further in view of Marimuthu (US 9,189,317 B1).
Regarding claim 11, the combination of Moran and Pandey differs from the claimed invention in not specifically disclosing that the operations comprise: storing one or more instances of sets of debugging information in a reserved portion of the set of memory components; receiving a new instance of an individual set of debugging information corresponding to the selected error handling mode; and replacing a target instance of the one or more instances stored in the reserved portion of the set of memory components with the new instance of the individual set of debugging information. However, Marimuthu teaches a problem monitoring system 110 to automatically detect problems by continuously monitoring components of the software product or periodically scanning the log files and audit files/database associated with the software product for any occurrence of errors; a debugging system 115 to gather a set of debug information, log file information, and environment details related to the problem; collects and packages the debug information received from debugging system 115 if the user detected issue is a new issue; and an update manager 135 to schedule periodic troubleshooting information updates or “on demand” updates in order to refresh the local troubleshooting information repository 140 with the latest problem signatures and troubleshooting task signatures (col. 3 line 62 through col. 4 line 25) in order to effectively collect the debug information. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Moran and Pandey in having that the operations comprise: storing one or more instances of sets of debugging information in a reserved portion of the set of memory components; receiving a new instance of an individual set of debugging information corresponding to the selected error handling mode; and replacing a target instance of the one or more instances stored in the reserved portion of the set of memory components with the new instance of the individual set of debugging information, as per teaching of Marimuthu, in order to effectively collect the debug information.
Allowable Subject Matter
Claims 5-8 and 12-18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach nor suggest “the operations comprise: selecting the second of the plurality of error handling modes in response to determining that the critical event trigger data corresponds to a non-fatal condition” as recited in claim 5; and “wherein the operations comprise: determining that a value associated with the target instance is lower than a value associated with the new instance, wherein the target instance is replaced in response to determining that the value associated with the target instance is lower than the value associated with the new instance” as recited in claim 12.
Claims 6-8 and 13-18 are also objected because of depending on claims 5 and 12, respectively, containing the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Thiruvengadam et al. (US 2024/0086075 A1) discloses management of error-handling flows in memory devices using probability data structure having a memory sub-system controller selecting the error-handling operation that corresponds to the smallest sum cost, and using the selected error-handling operation to update the error-handling flow ([0016]).
Orita et al. (US 2011/0161736 A1) discloses a debugging module that loads error decoding logic from firmware of the computing device, and thereafter executes the logic responsive to an error occurring within the computing device ([0003]-[0006]).
Richter et al. (US 2025/0028598 A1) discloses an error control component implemented in the memory system to enable error detection and correction of the configuration data, and communicating detected errors between the memory system and the host system improves transparency and communication of the system, thus improving reliability of the system (abstract and figure 5).
Desai et al. (US 2024/0264892 A1) discloses storage device non-fatal error debug system includes a storage device including a storage device chassis, storage device subsystems housed in the storage device chassis, and a non-fatal error debug subsystem provided in the storage device chassis and coupled to each of the storage device subsystems (abstract and figure 4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/ Primary Examiner, Art Unit 2133
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