DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim(s) 1-12 do not use “means for “(or “step for”) language, or generic placeholders for “means” coupled with functional language without recitation of sufficient structure for carrying out the claimed functions and therefore do not invoke 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6 and 10-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sawada, Ken (US-2023/0026792-A1).
[Claim 1] Regarding claim 1, Sawada teaches
a solid-state imaging element comprising (Sawada, in Figure 1, image sensing device 100):
for each pixel (Sawada, in Figure 1, pixel array 110 that include a plurality of unit imaging pixels),
a photoelectric conversion unit (Sawada, Figure 4, photoelectric conversion region PD, photoelectric conversion region (PD) may generate photocharges corresponding to incident light during an integration time where photocharges are accumulated. , paragraph 0087);
a first FD (Floating Diffusion) section (Sawada, in Figure 4, a floating diffusion region FD) that accumulates the electric charge transferred from the photoelectric conversion unit via a transfer transistor to convert the electric charge into a pixel signal (Sawada further teaches a transmission signal (TS) having an activation voltage level is applied to the transfer transistor (TX), photocharges generated by the photoelectric conversion region (PD) may be applied to the floating diffusion (FD) region, paragraph 0088) ;
a second FD section (Sawada, in Figure 5 teaches a contact region 216) that is connected to the first FD section via a connection transistor (Sawada in Figure 5 teaches that the first floating diffusion region FD is connected to the second floating diffusion region 216 via a switch transistor SW, paragraph 0093)
an inter-wire capacitor (Sawada, teaches in Figure 5, a metal-insulator-metal (MIM) capacitor 250 ), wherein the inter-wire capacitor (Sawada, Figure 5, metal-insulator-metal (MIM) capacitor 250 may be formed to have predetermined capacity, and may have, for example, a metal insulation metal (MIM) structure, paragraph 0054 ) wherein
the inter-wire capacitor is configured to include a first electrode (Sawada, teaches in Figure 5 a first electrode 258 of the metal-insulator-metal (MIM) capacitor 250 may be coupled to one terminal of the switch transistor SW and one terminal of the reset transistor RST, ( i.e. a second floating diffusion 216) that is connected to the second FD section (Sawada, in Figure 5, teaches second floating diffusion region 216 is connected to the first electrode of the metal-insulator-metal (MIM) capacitor 250, paragraph 0095), and
a second electrode (Sawada, the second electrodes 256a, 256b, 256c may be grounded,) that faces the first electrode across a dielectric (Sawada, teaches in some implementations, the capacitor may further include a dielectric region disposed between the first electrode and the second electrode, paragraph 0012) , and
when viewed in a plan view (Sawada, in Figure 3C, a plan view) from a logic substrate (Sawada, in Figure 5, a second substrate 230) that is stacked on a sensor substrate (Sawada, in Figure 5, a first substrate 210) on which the photoelectric conversion unit (Sawada, in Figure 5, a photoelectric conversion region 212) is provided, a wire (Sawada, in Figure 3C interconnect 258) connected to the second electrode (Sawada , in Figure 5, second electrodes 256a, 256b and 256c, ) is provided to cover at least the entire second electrode (Sawada, in Figure 5, the interconnect 258 appears to cover the entire second electrodes 256a, 256b and 256c).
[Claim 2]
Regarding claim 2, Sawada teaches all the limitations of claim 1, wherein the solid-state imaging element has a structure in which, when the photoelectric conversion unit is irradiated with light strong enough to exceed a saturation capacity of the photoelectric conversion unit, the electric charge overflowing from the photoelectric conversion unit is accumulated in the inter-wire capacitor, (Sawada teaches in Figures 4 and 5 that the capacitor 250 may store overflown charges, the amount of which exceeds capacitance of the floating diffusion (FD) region 214, and may be coupled to the floating diffusion (FD) region 214, so that the capacitor 250 can provide additional capacitance to the floating diffusion (FD) region 214. paragraph 0052). The charges in the floating diffusion node are transferred from the photoelectric conversion unit to floating diffusion.
[Claim 3]
Regarding claim 3, Sawada teaches all the limitations of claim 1, wherein a potential of the wire connected to the second electrode (Sawada, Figure 5, 256a, 256b, 256c) of the inter-wire capacitor is controlled to be at Lo level during a charge accumulation period in which the pixel is exposed to light for a long period of time and the electric charge is accumulated in the photoelectric conversion unit. Sawada teaches in Figure 5 a ground contact portion 252 may be formed of or include metal, and may be included in a second electrode of the capacitor 250, paragraph 0072. As such the second electrode of the inter-wire capacitor (i.e. the metal-insulator-metal (MIM) capacitor 250, Figure 5) is at low potential during a charge accumulation period.
[Claim 4]
Regarding claim 4, Sawada teaches all the limitations of claim 1, wherein the inter-wire capacitor and the wire are disposed in a wire layer on the sensor substrate side. Sawada teaches in Figure 5, that the inter-wire capacitor (i.e. a metal-insulator-metal (MIM) capacitor C250) is disposed on the sensor substrate (i.e. the first substrate layer 210) and the wire layer (i.e. the interconnect 252) is also in the sensor substrate (i.e. the first substrate layer 210) side.
[Claim 6]
Regarding claim 6, Sawada teaches all the limitations of claim 1, wherein the inter-wire capacitor is disposed in a wire layer on the sensor substrate side, and the wire is disposed in a wire layer on the logic substrate side.
Sawada further teaches the image sensing device that includes plurality of substrate layers and interconnect layers as shown in Figure 5. The unit pixel is formed across the first substrate layer 210 (i.e. sensor layer 210) and a first interconnect layer 220, a second substrate layer 230 (i.e. logic substrate) and a second interconnect layer 240. Sawada further teaches a capacitor 250 electrically coupled to the floating diffusion region by the switch transistor gate. The capacitor may include a first electrode and a second electrode that are disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer, wherein a portion of the first interconnect layer, a portion of the second substrate layer, and a portion of the second interconnect layer are disposed between the first electrode and the second electrode, paragraph 0006. Sawada further teaches the capacitor 250 may be formed to have predetermined capacity, and may have, for example, a metal insulation metal (MIM) structure, paragraph 0054. Sawada teaches the capacitor 250 may be disposed in the sensor substrate side, however, and includes a wire layer (Sawada, Figure 5), connecting the first electrode 258 in the interconnect layer of the logic substrate (i.e. second substrate 230).
[Claim 10]
Regarding claim 10, Sawada teaches all the limitations of claim 1, wherein further comprising an overflow transistor (Sawada, Figure 4, the switch transistor SW) that, when the photoelectric conversion unit is irradiated with light strong enough to exceed a saturation capacity of the photoelectric conversion unit, causes the electric charge overflowing from the photoelectric conversion unit to overflow and to be accumulated in the inter-wire capacitor, (Sawada teaches in Figures 4 and 5 that the capacitor 250 may store overflown charges, the amount of which exceeds capacitance of the floating diffusion (FD) region 214, and may be coupled to the floating diffusion (FD) region 214, so that the capacitor 250 can provide additional capacitance to the floating diffusion (FD) region 214. paragraph 0052).
[Claim 11]
Regarding claim 11, Sawada teaches all the limitations of claim 1, wherein the inter-wire capacitor is configured in a three-dimensional structure. Sawada teaches the inter-wire capacitor (i.e. a metal-insulator-metal (MIM) capacitor 250 in Figure 5) and the wiring is comprised of two electrodes (Sawada, Figure 5, a first electrode 258 and a second electrode 256a, 256b and 256c) and a dielectric (i.e. the dielectric between the TSVs 254a, 254b, 254c and 256a, 256b, 256c) that are fabricated in three dimensional structure. Sawada describes the image sensing device 100 that includes the capacitor 250 which may a MIM capacitor that includes a dielectric in between them. The structure of a MIM capacitor is a three dimensional structure fabricated in wafer or stacked wafers.
[Claim 12]
Regarding claim 1, Sawada teaches an electronic device (Sawada, teaches an image sensing device 100 in Figure 1) comprising a solid-state imaging element including:
for each pixel (Sawada, teaches in Figure 1, pixel array 110 that include a plurality of unit imaging pixels), a photoelectric conversion unit that photoelectrically converts light into an electric charge(Sawada, Figure 4, photoelectric conversion region PD, photoelectric conversion region (PD) may generate photocharges corresponding to incident light during an integration time where photocharges are accumulated, paragraph 0087);
a first FD (Floating Diffusion) section (Sawada, in Figure 4, a floating diffusion region FD) that accumulates the electric charge transferred from the photoelectric conversion unit via a transfer transistor to convert the electric charge into a pixel signal (Sawada further teaches a transmission signal (TS) having an activation voltage level is applied to the transfer transistor (TX), photocharges generated by the photoelectric conversion region (PD) may be applied to the floating diffusion (FD) region, paragraph 0088) ;
a second FD section (Sawada, in Figure 5 teaches a contact region 216) that is connected to the first FD section via a connection transistor (Sawada, in Figure 5 teaches that the first floating diffusion region FD is connected to the second floating diffusion region 216 via a switch transistor SW, paragraph 0093); and
an inter-wire capacitor (Sawada, teaches in Figure 5, the metal-insulator-metal (MIM) capacitor 250), wherein the inter-wire capacitor (Sawada, Figure 5, the metal-insulator-metal (MIM) capacitor 250 may be formed to have predetermined capacity, and may have, for example, a metal insulation metal (MIM) structure, paragraph 0054 ), wherein
the inter-wire capacitor is configured to include a first electrode (Sawada, teaches in Figure 5 a first electrode 258 of the capacitor C 250 may be coupled to one terminal of the switch transistor SW and one terminal of the reset transistor RST, ( i.e. a second floating diffusion 216) that is connected to the second FD section (Sawada, in Figure 5, teaches second floating diffusion region 216 is connected to the first electrode of the capacitor C 250, paragraph 0095) and
a second electrode (Sawada, the second electrodes 256a, 256b, 256c may be grounded,) that faces the first electrode across a dielectric (Sawada, teaches in some implementations, the capacitor may further include a dielectric region disposed between the first electrode and the second electrode, paragraph 0012) , and
when viewed in a plan view (Sawada, in Figure 3C, a plan view) from a logic substrate (Sawada, in Figure 5, a second substrate 230) that is stacked on a sensor substrate (Sawada, in Figure 5, a first substrate 210) on which the photoelectric conversion unit (Sawada, in Figure 5, a photoelectric conversion region 212) is provided, a wire (Sawada, in Figure 3C, interconnect 252) connected to the second electrode (Sawada , in Figure 5, second electrodes 256a, 256b and 256c, ) is provided to cover at least the entire second electrode (Sawada, in Figure 3B, the wire 252 appears to cover the entire second electrodes 256a, 256b and 256c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sawada, Ken (US-2023/0026792-A1) in view of Mabuchi et al. (US-2024/0015414-A1)
[Claim 5]
Regarding claim 5, Sawada teaches all the limitations of claim 1, Sawada teaches all the limitations of claim 1.
Sawada does not teach, wherein the inter-wire capacitor and the wire are disposed in a wire layer on the logic substrate side.
Mabuchi teaches a similar image sensor device (Mabuchi, in Figure 2C teaches a pixel circuit 204C) that pixel array 102 is implemented on a pixel wafer or a sensor wafer, and readout circuit 106, control circuit 110 and function logic 108 are implemented on an application specific integrated circuit (ASIC) wafer, where the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through substrate vias (TSVs). For another example, pixel array 102 and control circuit 110 are implemented on a pixel wafer, and array of capacitors, readout circuit 106, and function logic 108 are implemented on an ASIC wafer, where the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through substrate vias (TSVs), paragraph 0025. The substrate (i.e. logic substrate) for the read out integrated circuit (i.e. 2nd pixel wafer as illustrated in Mabuchi, Figure 2C). The capacitor 240 is connected to a supply voltage VRFD and a third floating diffusion node FD3 that is connected to a second diffusion node FD2 via a connection transistor (Mabuchi, Figure 2C, a capacitor readout transistor 238) and the second floating diffusion node FD2 is connected to a first floating diffusion node FD1 via a connection transistor (Mabuchi, in Figure 2C, a dual floating diffusion transistor 224). The capacitor 240 is comprised of a MIM capacitor (Mabuchi, Figure 2C, the capacitor CAP 240 is a lateral overflow integration capacitor (LOFIC) that may be implemented with a metal-oxide-semiconductor capacitor (MOSCAP), a metal-insulator-metal (MIM) capacitor, a high k MIM capacitor, or the like, paragraph 0032). The capacitor 240 is disposed on the second pixel wafer and the wire layers are disposed on this wafer as outlined via dotted line in Figure 2C. The substrate of the second pixel wafer is in a different substrate than the first pixel wafer, where the photodiode and transfer transistors are disposed on a different substrate (i.e. sensor substrate).
Mabuchi teaches in one of the embodiments n Figure. 2C, pixel circuit 204C includes circuit elements that are included among a first wafer 246 (e.g., a sensor wafer) and a second wafer 248 (e.g., a logic wafer). In one example, the first wafer 246 and the second wafer 248 are coupled together or stacked together in a stacked chip scheme to provide a complementary metal oxide semiconductor (CMOS) image sensor (CIS) in accordance with the teachings of the present invention. In one example, a second wafer may further include column circuitry, row circuitry, control circuitry, ASIC processing circuitry, etc. paragraph 0042.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sawada with Mabuchi to implement sensitive photodiodes in one wafer or substrate and a read out circuits in another wafer or substrate.
[Claim 7]
Regarding claim 7, Sawada teaches all the limitations of claim 1.
Sawada does not teach wherein the pixel includes a second photoelectric conversion unit having a smaller light-receiving area than the photoelectric conversion unit, and a third FD section that accumulates an electric charge photoelectrically converted by the second photoelectric conversion unit to convert the electric charge into a pixel signal, wherein the inter-wire capacitor is connected to the third FD section via a second connection transistor.
Mabuchi teaches in one of the embodiments in Figure. 2C, pixel circuit 204C that includes a second photoelectric conversion unit 228 SPD that has a smaller light receiving area ( hence named Smaller Photo Diode SPD, Mabuchi, a second photodiode SPD 228, the second photodiode 228 has smaller sensing area and may therefore be referred to as a small photodiode (SPD) that has a lower sensitivity to light, paragraph 0028) and a third floating diffusion unit FD3 that accumulates an electric charge photoelectrically converted by the second conversion unit to convert the electric charge into a pixel signal, wherein the inter-wire capacitor (i.e. capacitor 240) is connected to the third floating diffusion (i.e. floating diffusion FD3) via a second transistor (i.e. a capacitor readout transistor 238).
Mabuchi teaches the use of a second photodiode SPD 228, the second photodiode 228 has smaller sensing area and may therefore be referred to as a small photodiode (SPD) that has a lower sensitivity to light compared to the first photodiode LPD 214. The second photodiode 228 may be configured for sensing bright or strong light. The first photodiode 214 and the second photodiode 228 may be configured to have different full well capacity such as different implant configurations (e.g., dosage, implant energy that result in having different volume of depletion region, paragraph 0028.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sawada with Mabuchi with the motivation to implement a photodiode that has lower sensitivity to light compared to the first photodiode which has a higher sensitivity to light, paragraph 0028.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sawada, Ken (US-2023/0026792-A1) in view of Mabuchi et al. (US-2024/0015414-A1) and further in view of Du, et al. (US-2024/0244344-A1)
[Claim 8]
Regarding claim 8, Sawada in view of Mabuchi teach all the limitations of claim 7.
Sawada in view of Mabuchi do not teach further comprising a second inter-wire capacitor including a third electrode that is connected to the third FD section and a fourth electrode that faces the third electrode across a dielectric.
Du teaches a similar imaging element (Du, in Figure 1, imaging system 100) that includes a pixel circuit 204 (Du, Figure 2) a second inter-wire capacitor (Du, Figure 2, capacitor 254) that is connected to a third floating diffusion FD3 (Du. Figure 2). Du further teaches each of the main LOFIC 252 and the subordinate LOFICs 254-n is implemented with a metal-insulator-metal (MIM) capacitor including a high dielectric or high-k insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first metal electrode and the second metal electrode of the main LOFIC 252 and subordinate LOFICs 254-n may be formed of a single layer of high-k material or a multiple layer stack of high-k material, paragraph 0037. Therefore, the second inter-wire capacitor (i.e. capacitors 254-n, in Figure 2) is comprised of a third electrode (i.e. the second metal electrode) and a fourth metal electrode (i.e. first metal electrode) that is connected to the third floating diffusion.
Du teaches using a second capacitor in the imaging system with a lateral overflow integration capacitor LOFIC network providing reduced image lag. Du further teaches that LOFICs may be included in pixel circuits to increase the full well capacity of the pixel circuits and thereby increase high dynamic range capabilities of corresponding image sensors, paragraph 0017.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sawada and Mabuchi with Du with the motivation to increase the full well capacity of the pixel circuits and thereby increase high dynamic range capabilities of corresponding image sensors, paragraph 0017.
Allowable Subject Matter
Claim 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
[Claim 9]
Regarding claim 9, prior art fails to tech or reasonably suggest wherein the inter-wire capacitor and the second inter-wire capacitor are covered by one of a wire connected to the second electrode of the inter-wire capacitor and a wire connected to the third electrode of the second inter-wire capacitor when viewed in a plan view from the logic substrate.
Sawada teaches the first inter-wire capacitor (Sawada, Figure 5, a metal-insulator-metal (MIM) capacitor 250) is covered by one of a wire (Sawada, in Figure 3B interconnect 252) connected to the second electrode (Sawada , in Figure 5, second electrodes 256a, 256b and 256c, ) is provided to cover at least the entire second electrode (Sawada, in Figure 3B, the wire 252 appears to cover the entire second electrodes 256a, 256b and 256c).
Mabuchi teaches a second inter-wire-capacitor, however, the combination of Sawada, Mabuchi and Du fail to teach or reasonably suggest the second inter-wire-capacitor are covered by one of a wire connected to the second electrode of the inter-wire capacitor and a wire connected to the third electrode of the second inter-wire capacitor when viewed in a plan view from the logic substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The following show additional prior art systems/methods for imaging apparatus:
KWON; Young-Jun US-20170345854-A1
KATO; ATSUSHI US-20230007202-A1
SEKINE; HIROSHI US-20240178244-A1
Kim; Jungsan US-20240258354-A1
Liu; Yuanliang US-20250126373-A1
Shim; Eun Sub US-20240379719-A1
KIM; Juyeong US-20240088176-A1
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/MEHEDI NMN HASSAN/Examiner, Art Unit 2637
/SINH TRAN/
Supervisory Primary Examiner, Art Unit 2637
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