DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy of Japanese patent application number 2022-134406, filed on August 25, 2026, has been received and made of record.
Information Disclosure Statement
The information disclosure statement (lDS) submitted on February 17, 2025 is in compliance with the provisions of 37 CFR 1.97 and has been considered by the Examiner.
The information disclosure statement filed February 17, 2025 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein that lacks a legible copy has not been considered. Specifically, cited foreign patent document no. JP 20060033452 A, and cited foreign patent document no. WO 2016009832 A1 have not been submitted.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “first switching element” and “second switching element” in claims 17-19.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9-10, 13, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsunai (JP 2013-255035 A). The Examiner also notes, with respect to Tsunai, that for purposes of examination, the Examiner will refer to the machine translation.
In regard to claim 1, note Tsunai discloses a light detection element comprising a plurality of pixels arranged in a matrix (paragraph 0008-0010, and figures 1-2: 100), wherein the plurality of pixels includes a photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal (paragraphs 0018, 0021, 0025, and figure 6: 104, 131, 132; each of the pixels 131 and 132 includes photoelectric conversion circuits 104), a signal processing circuit that outputs a converted pixel signal (paragraphs 0037-0043, 0047, and figure 6: 412, 422; the pixel signals are processed by signal processing units 412 and 422), a storage circuit that stores data of an output signal of the signal processing circuit (paragraphs 0037-0043, 0047, and figure 6: 414; the storage unit 414 includes memory elements for storing values for each photoelectric signal), and a switching circuit that switches an output destination of the analog pixel signal or the output signal to share the storage circuit among the plurality of pixels (paragraphs 0037-0043, 0047, and figure 6: 411, 421, 413, 423; the switches 411 and 421, and the demultiplexers 413 and 423 are used to control which of the processing circuits and memory elements are chosen for processing and storage of the signals).
Therefore, it can be seen that the primary reference fails to explicitly disclose that the signal processing circuit of the plurality of pixels include a comparator that outputs a result of comparing the analog pixel signal with a reference signal.
Official Notice is taken that the concepts and advantages of the use of a comparator that outputs a result of comparing the analog pixel signal with a reference signal are notoriously well known and expected in the art in order to convert the analog pixel signal into a digital value for storage/reproduction. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the primary reference such that the pixels include a comparator that outputs a result of comparing the analog pixel signal with a reference signal, in the art in order to convert the analog pixel signal into a digital value for storage/reproduction, as is well known in the art.
In regard to claim 2, note Tsunai discloses the switching circuit is arranged on an output terminal side of the comparator (paragraphs 0040-0042, 0047, and figure 6: 413, 423; the demultiplexers 413 and 423 perform switching of the output of the signal processing circuits 412 and 422).
In regard to claim 3, note Tsunai discloses the switching circuit is arranged on an input terminal side of the comparator (paragraphs 0040-0042, 0047, and figure 6: 411, 421; the switches 411 and 421 perform switching of the input provided to the signal processing circuits 412 and 422).
In regard to claim 9, note Tsunai discloses that the switching circuit switches an output destination of the analog pixel signal or the output signal to cause pixels adjacent to each other to share the storage circuit, among the plurality of pixels (paragraphs 0037-0043, 0047, and figure 6: 411, 421, 413, 423; the switches 411 and 421, and the demultiplexers 413 and 423 are used to control which of the processing circuits and memory elements are chosen for processing and storage of the signals).
In regard to claim 10, note Tsunai discloses that the plurality of pixels individually receives beams of light of a plurality of colors, and the storage circuit is shared by pixels that receive light of an identical color (paragraphs 0018, 0021, 0025, and figure 6: 131, 132, 414; each of the pixels 131 and 132 are considered to be identical, wherein they each receive light of identical color signals that are stored in the storage circuit 414).
In regard to claim 13, note Tsunai discloses that the plurality of pixels includes a first pixel to a fourth pixel arranged close to each other (paragraphs 0018, 0021, 0025, and figure 6: 104, 131, 132; each of the pixels 131 and 132 includes a plurality of photoelectric conversion circuits 104 close to each other), the storage circuit includes a first latch circuit, and a number of pixels sharing the first latch circuit is variable among the first pixel to the fourth pixel (paragraphs 0037-0043, 0047, and figure 6: 411, 421, 413, 423, 414; the switches 411 and 421, and the demultiplexers 413 and 423 are used to control which of the processing circuits and memory elements 414 are chosen for processing and storage of the signals).
In regard to claim 16, note Tsunai discloses that the switching circuit includes a multiplexer (paragraphs 0040-0042, 0047, and figure 6: 413, 423; the demultiplexers 413 and 423 perform switching of the output of the signal processing circuits 412 and 422).
In regard to claim 17, note Tsunai discloses that the switching circuit includes a first switching element that switches whether or not to output the analog pixel signal to a first pixel among the plurality of pixels, and a second switching element that switches whether or not to output the analog pixel signal to a second pixel different from the first pixel (paragraphs 0040-0042, 0047, and figure 6: 411, 421; the switches 411 and 421 perform switching of the input provided to the signal processing circuits 412 and 422).
In regard to claim 20, note Tsunai discloses an electronic device comprising a plurality of pixels arranged in a matrix (paragraph 0008-0010, figures 1-2: 100, and figure 4), wherein the plurality of pixels includes a photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal (paragraphs 0018, 0021, 0025, and figure 6: 104, 131, 132; each of the pixels 131 and 132 includes photoelectric conversion circuits 104), a signal processing circuit that outputs a converted pixel signal (paragraphs 0037-0043, 0047, and figure 6: 412, 422; the pixel signals are processed by signal processing units 412 and 422), a storage circuit that stores data of an output signal of the signal processing circuit (paragraphs 0037-0043, 0047, and figure 6: 414; the storage unit 414 includes memory elements for storing values for each photoelectric signal), and a switching circuit that switches an output destination of the analog pixel signal or the output signal to share the storage circuit among the plurality of pixels (paragraphs 0037-0043, 0047, and figure 6: 411, 421, 413, 423; the switches 411 and 421, and the demultiplexers 413 and 423 are used to control which of the processing circuits and memory elements are chosen for processing and storage of the signals).
Therefore, it can be seen that the primary reference fails to explicitly disclose
that the signal processing circuit of the plurality of pixels include a comparator that outputs a result of comparing the analog pixel signal with a reference signal.
Official Notice is taken that the concepts and advantages of the use of a comparator that outputs a result of comparing the analog pixel signal with a reference signal are notoriously well known and expected in the art in order to convert the analog pixel signal into a digital value for storage/reproduction. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the primary reference such that the pixels include a comparator that outputs a result of comparing the analog pixel signal with a reference signal, in the art in order to convert the analog pixel signal into a digital value for storage/reproduction, as is well known in the art.
Allowable Subject Matter
Claims 4-8, 11-12, 14-15, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2016/0198115: note the use of an image sensor having a plurality of pixels that share a comparator, and controlling the storage of each pixel signal in a shared storage circuit.
US 2023/0092325: note the use of an image sensor having a plurality of pixels that share a comparator, and controlling the storage of each pixel signal in a shared storage circuit.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at (571) 272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISS S YODER III/Examiner, Art Unit 2638
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