DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/17/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 13 recites the limitation "the signal line reset level generating unit" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koh et al. (US 2017/0134681 A1, hereinafter “Koh”).
Regarding claim 1, Koh discloses an imaging device (Figs. 1 & 2) comprising:
a pixel array unit (110) in which pixels are arranged in a matrix in a row direction and a column direction (Figs. 1 & 2, par. [0045]-[0046]);
a signal line (C1 … C7) that transmits signals read out from the pixels in the column direction (Fig. 2, par. [0047]);
a sample-and-hold switch (e.g., TR4 in Fig. 3A, or TR8 in Fig. 3B) that samples and holds the signals, which are transmitted via the signal line, for each column (Fig. 2 and par. [0062]-[0065], [0067]-[0071]. It should be noted that the transistor switch TR4 or TR8 acts as a sample-and-hold switch as it controls selection for sampling of signal to the corresponding column line. This similar sampling switch is also discussed in the Applicant’s own specification); and
a connection switch (e.g., S1 controlled by signal AVG in Fig. 2) that connects signal lines of different columns (e.g., C1 and C3) in which the signals are sampled and held (par. [0074] & [0103], wherein the connection switch S1 is turned on in a binning mode to combine image signals from column C1 and C3. Similarly, S2 and S3 perform a similar operation to combine image signals from other columns).
Regarding claim 2, Koh further discloses an AD conversion unit (located within 130 as shown in Figs. 1 and 4) that performs AD conversion for each of the columns of the signals transmitted via the signal line; and an active control unit (from column scanning circuit 140) that activates one AD conversion unit out of the AD conversion units of each column connected via the connection switch (see par. [0081], wherein one of the ADCs is activated by a selection signal from the column scanning circuit 140 to convert the image signals combined from two columns into a digital signal).
Regarding claim 3, as clearly disclosed by Koh in Fig. 4, the AD conversion unit comprises: a comparator (131) that compares a potential of the signal line (C1) with a ramp signal (VRAMP); and a counter (132) that performs a counting operation, based on a comparison result from the comparator (Fig. 4 and par. [0077]-[0078]).
Regarding claim 4, it is seen in Koh that the active control unit controls the AD conversion units, separately, for columns to be activated and columns to be deactivated (see par. [0081]).
Regarding claim 10, Koh also discloses that the sample-and-hold switch is a transistor provided for each signal line (see Fig. 3A or 3B. Note transistor TR4 or TR8).
Claims 1-10, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi (US 2018/0249110 A1).
Regarding claim 1, Kobayashi discloses an imaging device (Figs. 5 & 6) comprising:
a pixel array unit (1) in which pixels are arranged in a matrix in a row direction and a column direction (Figs. 5 & 6);
a signal line (L1 or L2) that transmits signals read out from the pixels in the column direction (Figs. 5 & 6);
a sample-and-hold switch (M4A or M4B respectively connected to the signal L1 or L2) that samples and holds the signals, which are transmitted via the signal line, for each column; and a connection switch (M30) that connects signal lines of different columns (L1 and L2) in which the signals are sampled and held (see Figs. 5 & 6 and par. [0064]-[0072]. In an addition readout mode, image signals from photoelectric conversion units 11A and 11B are added using the connection switch M30 before inputting into the comparator for digital conversion. It should be noted that the selection transistor M4A or M4B acts as a sample-and-hold switch as it controls selection for sampling of signal to the corresponding column line. This similar sampling switch is also discussed in the Applicant’s own specification).
Regarding claim 2, Kobayashi also discloses an AD conversion unit (3) that performs AD conversion for each of the columns of the signals transmitted via the signal line; and an active control unit (4) that activates one AD conversion unit out of the AD conversion units of each column connected via the connection switch (see par. [0040], [0060]-[0061] and [0081]-[0082], wherein at least one AD conversion unit is activated by one of the power control signals PWR1, PWR2 or PWR3 depending on a readout mode).
Regarding claim 3, also disclosed by Kobayashi is a comparator (A1 and/or A2) that compares a potential of the signal line with a ramp signal (RAMP); and a counter that performs a counting operation, based on a comparison result from the comparator (see par. [0044]-[0045]).
Regarding claim 4, it is also seen in Kobayashi that the active control unit controls the AD conversion units, separately, for columns to be activated and columns to be deactivated (see par. [0040], [0060]-[0061] and [0081]-[0082] in which AD conversion units are selectively activated by power signals PWR1, PWR2 and PWR3 depending on a readout mode. Some AD conversion units are not activated in a focus detection mode to reduce power consumption).
Regarding claim 5, Kobayashi further discloses a first DC-cut capacitor (e.g., C11 or C21 in Fig. 5) connected to a first input terminal of the comparator; and a second DC-cut capacitor (e.g., C13 or C23) connected to a second input terminal of the comparator (see Fig. 5. Note that all input capacitors shown in the illustrated figures in Kobayashi are coupling capacitors which are also known as DC-cut capacitors for cutting DC components).
Regarding claim 6, as seen in Fig. 5 of Kobayashi, a changeover switch (M31) that switches between the first input terminal of the comparator and a ground a connection destination of a second capacitance electrode of the first DC-cut capacitor (C21) having a first capacitance electrode being connected to the signal line.
Regarding claim 7, Kobayashi further discloses the active control unit (4) to control the changeover switch (using control signal ADDB), separately, for columns to be activated and columns to be deactivated (see Fig. 5 and par. [0066]-[0067]).
Regarding claim 8, Kobayashi further discloses an amplifier (e.g., A11 and/or A12 shown in Fig. 6 which is similar to Fig. 5 with amplifiers added to the column circuits) that amplifies, for each column, signals transmitted via the signal line and inputs the amplified signals to the AD conversion unit (see Fig. 6 and par. [0069]-[0070]).
Regarding claim 9, as also disclosed by Kobayashi, the active control unit (4) controls the amplifier (via power signals PWR1, PWR2), separately, for columns to be activated and columns to be deactivated (Fig. 6 and par. [0072]).
Regarding claim 10, it is seen in Kobayashi that the sample-and-hold switch (M4A, M4B) is a transistor provided for each signal line (L1, L2, respectively).
Regarding claim 18, Kobayashi also discloses that the pixel comprises: a photodiode (11A or 11B); a transfer transistor (M1A or M1B) that transfers charges stored in the photodiode to a floating diffusion (12A or 12B); a reset transistor (M2A or M2B) that resets the floating diffusion; an amplification transistor (M3A or M3B) that outputs a signal corresponding to a potential of the floating diffusion; and a selection transistor (M4A or M4B) connected between the amplification transistor and the signal line (L1 or L2) (see Figs. 5 & 6 and par. [0035]).
Regarding claim 19, as discussed in claim 1 above, the sample-and-hold switch (M4A or M4B) is the selection transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of Yonemoto (US 2007/0222876 A1).
Regarding claim 14, Kobayashi is silent as to a capacitance used for sampling and holding the signal is a parasitic capacitance of the signal line. However, as taught by Yonemoto, the column signal line (e.g., VSIGn) is made into a floating state in a sampling phase, and the parasitic capacity of the column signal line VSIGn is used as the capacitance for sampling and holding (Yonemoto, Figs. 6, 7, 11 & 12 and par. [0097]).
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings from Kobayashi and Yonemoto to use parasitic capacitance of the column line as sampling capacitance in a conventional fashion without departing from the scope of the invention.
Regarding claim 15, it is seen in the combination of Kobayashi and Yonemoto that the connection switch (M30 in Figs. 5 & 6 of Kobayashi) is connected, in series, to a capacitance for each column (parasitic capacitance of each column discussed in claim 14) used for sampling and holding the signal.
Regarding claim 16, the combined teaching of Kobayashi and Yonemoto further discloses that the connection switch is connected, in parallel, to a capacitance for each column used for sampling and holding the signal (see Yonemoto, Figs. 1 & 6 and note sampling capacitance CSH used for sampling and holding the signal and connected in parallel to the connection switch when combined with the teaching of Kobayashi).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of Wakashima (US 2021/0067721 A1).
Regarding claim 12, Kabayashi is silent about a signal line reset transistor that resets the potential of the signal line; and a signal line reset level generating unit that generates a reset level of the potential of the signal line. Wakashima, on the other hand, teaches this feature as shown in Fig. 2 where a column line reset transistor (231) is provided for resetting the potential of column output line (104) to the level generated by output line reset generation circuit (123) (see Wakashima, Fig. 2 and par. [0036]).
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings from Kobayashi and Wakashima to arrive at the Applicant’s claimed invention for resetting the column signal line to provide optimal control of signal readout.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of Ishii (US 2012/0327280 A1).
Regarding claim 20, although Kobayashi fails to teach a binning transistor that connects floating diffusion of different rows, such a binning transistor is well known in the art to connect floating diffusions of pixels of different rows as taught by Ishii to improve signal-to-noise ratio (see Ishii, Fig. 3, transistor 308, par. [0040]). For that reason, one of ordinary skill in the art would have been motivated to modify the imaging device in Kobayashi in view of Ishii to provide a binning transistor as claimed so that multiple pixels of different rows would be binned (added) to improve signal-to-noise ratio, thereby improving image quality.
Allowable Subject Matter
Claims 11 and 17 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art references of record, either alone or in combination, fail to teach or suggest “a driver that drives the transistor from both sides in the row direction.”
Regarding claim 17, the prior art references of record, either alone or in combination, also fail to teach or suggest “a constant current transistor electrically connectable to the signal line and passing a constant current, based on a source follower formed between the signal line and the pixel, wherein the constant current transistor is turned on during constant current readout, and the constant current transistor is turned off during capacitive load readout.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHAN T TRAN whose telephone number is (571)272-7371. The examiner can normally be reached Monday - Friday, 9:00am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NHAN T TRAN/ Primary Examiner, Art Unit 2638
Prosecution Insights