Prosecution Insights
Last updated: July 17, 2026
Application No. 19/105,368

DISPLAY DEVICE, ELECTRONIC APPARATUS, AND DRIVING METHOD OF DISPLAY DEVICE

Non-Final OA §103
Filed
Feb 21, 2025
Priority
Aug 30, 2022 — JP 2022-137207 +1 more
Examiner
TRUONG, NGUYEN H
Art Unit
2623
Tech Center
2600 — Communications
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
1y 5m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
292 granted / 491 resolved
-2.5% vs TC avg
Strong +18% interview lift
Without
With
+17.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
16 currently pending
Career history
515
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
91.8%
+51.8% vs TC avg
§102
4.2%
-35.8% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 491 resolved cases

Office Action

§103
CTNF 19/105,368 CTNF 87848 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priorities 02-27 AIA Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2022-137207 , filed on 08/30/2022 . Information Disclosure Statement The information disclosure statements filed 02/21/2025 has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence. Election/Restrictions In response to a Requirement for Restriction/Election dated 12/18/2025; the Office acknowledges that the Applicant elected species I, without traverse, encompassing claims 1-13. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-4, 6, 8-10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park’954 et al. (US Pub. 2017/0124954 A1, hereinafter referred to as “Park’954”) in view of Song et al. (US Pub. 2022/0343844 A1) . Regarding claim 1 ; Park’954 teaches a display device (a display device, Figs.20 and 26) comprising: PNG media_image1.png 502 520 media_image1.png Greyscale (Fig.20 of Park’954 reproduced) a plurality of signal lines extending along a first direction (Fig. 26, a plurality of data lines DL along a vertical direction are connected between a data driver 1730 and a plurality of pixels PX a display panel 1710) ; a plurality of control lines extending along a second direction different from the first direction (Fig.26; a plurality of control lines (e.g., scan lines, compensation control signal lines GC, initialization control signal lines GI, and emission control signal lines EM) along a horizontal direction are connected between a scan driver 1750, a control driver 1770, and the plurality of pixels PX in the display panel 1710) ; a plurality of pixels (a plurality of pixels PX, Fig.26) ; and a drive unit (a driving circuit comprises the data driver 1730, the scan driver 1750, and the control driver 1770; Fig.26) that drives the plurality of pixels (para. [0175]) , wherein each of the plurality of pixels (Fig.20 reproduced above shows a pixel circuit 1300) includes a light emitting element (a light emitting diode OLED) , a capacitor (a storage capacitor CST) , a write transistor (a scan transistor 1310) that causes a voltage corresponding to a pixel signal supplied from a corresponding signal line among the plurality of signal lines to be accumulated in the capacitor (para. [0072], the storage capacitor CST may store a voltage (e.g., a data voltage VDATA) transferred from the data line DL by the scan transistor 1310) , a drive transistor (a driving transistor 1330) that supplies a current corresponding to the voltage accumulated in the capacitor to the light emitting element (para. [0074], the driving transistor 1330 may generate a driving current based on the data voltage VDATA stored in the storage capacitor CST) , and an initialization transistor (an initialization transistor 1370) in which one of a source node and a drain node is provided to be connectable to an anode of the light emitting element (see Fig.20, a drain electrode of the initialization transistor 1370 is connected to an anode of the light emitting diode OLED (i.e., node N3)) , and the drive unit turns off the initialization transistors provided in all of the plurality of pixels at or before a timing at which the light emission control transistors provided in pixels that simultaneously emit light among the plurality of pixels are turned on (Fig.21, one frame comprises an off-bias and initialization period TINIT, a VTH compensation period TCOMP, a data writing period TWRITE, an anode initialization period TINIT2, and an emission period TEMI. In the anode initialization period TINIT2, para. [0079], an initialization control signal GI may be a global control signal that is concurrently (e.g., substantially simultaneously) applied to all of the pixels included in the organic light emitting diode display device. In the anode The initialization control signal GI transitions from a low level (i.e., turn on the initialization transistor 1470) to a high level (i.e., turn off the initialization transistor 1470) before a start time of the emission period TEMI). In the first embodiment, Park’954 does not teach the initialization transistor comprising the other of the source node and the drain node is provided to be connectable to a cathode of the light emitting element . In a second embodiment, Park’954 teaches that the initialization transistor comprising the other of the source node and the drain node is provided to be connectable to a cathode of the light emitting element (Fig.15, an initialization transistor 970 comprises a source electrode connected to a cathode of the light emitting diode OLED). At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the first embodiment of Park’954 to include the teaching of the second embodiment of Park’954 of connecting a source electrode of an initialization transistor to a cathode of the light emitting diode OLED. As such, the node N3 would be initialized by the second power supply voltage ELVSS. The motivation would have been in order to simplify the pixel driving circuit. Park’954 does not explicitly teach a light emission control transistor that controls whether or not to supply the current corresponding to the voltage accumulated in the capacitor from the drive transistor to the light emitting element . Song teaches a light emission control transistor (first and second emission control switching elements T5 and T6; Fig.2) that controls whether or not to supply the current corresponding to the voltage accumulated in the capacitor from the drive transistor to the light emitting element (Fig.3, para. [0105-0106], one frame comprises a first period DU1, a second period DU2, a third period DU3, and a fourth period DU4. The emission control switching elements T5 and T6 are turned off during the first period DU1, the second period DU2, and the third period DU3. The emission control switching elements T5 and T6 are turned on during the fourth period DU4 which is an emission period). At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Park’954 of defining an emission period by reducing a voltage level of the second power supply voltage ELVSS to include the teaching of Song of providing emission control transistors which are configured to define an emission period. Accordingly, in the display device of Park’954 as modified by Song, the emission control transistors would be turned off in the off-bias and initialization period TINIT, the VTH compensation period TCOMP, the data writing period TWRITE, and the anode initialization period TINIT2. The emission control transistors would be turned on during the emission period TEMI. The motivation would have been in order to reduce leakage current through the driving transistor. Regarding claim 2 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 further teaches the drive unit turns off the initialization transistors provided in all of the plurality of pixels within a period from a timing at which the write transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned on to the timing of an emission period of all pixels (Fig.21, the anode initialization period TINIT2 is performed between the data writing period TWRITE and the emission period TEMI. Therefore, the initialization transistors are turned off within the anode initialization period from a timing at which the scan transistors 1410 are turned on to write data voltage to the storage capacitor CST to the start timing of the emission period TEMI. The scan transistor 1310 is turned on to supply a data voltage to the storage capacitor CST). Park’954 does not teach turning on the light emission control transistors. Song teaches turning on the light emission control transistors in an emission period (see the analysis of claim 1, Song discloses that the emission control transistors are configured to turn on to define an emission period). Accordingly, the combination of Park’954 and Song further teaches the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned on . The motivation is the same as the rejection of claim 1. Regarding claim 3 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 further teaches the drive unit simultaneously turns off the initialization transistors provided in all of the plurality of pixels (Fig.21, para. [0079 and 0087], the initialization control signal GI is a global control signal. The initialization control signal GI has a high value during the emission period TEMI). Regarding claim 4 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 further teaches the drive unit simultaneously turns off the initialization transistors provided in all of the plurality of pixels at the timing of the emission period (Fig.21, para. [0079 and 0087], the initialization transistors 1370 are turned off at the timing at the start time of the emission period). Park’954 does not teach turning on the light emission control transistors. Song teaches turning on the light emission control transistors in an emission period (see the analysis of claim 1, Song discloses that the emission control transistors are configured to turn on to define an emission period). Accordingly, the combination of Park’954 and Song further teaches the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned on . The motivation is the same as the rejection of claim 1. Regarding claim 6 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 further teaches the drive unit turns on the initialization transistors provided in all of the plurality of pixels at or after the emission period (Fig.21, para. [0079 and 0087], in the anode initialization period ITINT2, the initialization transistors 1370 are turned on before the emission period. In other words, the initialization transistors are turned off after the emission period of previous frame). Park’954 does not teach turning off the light emission control transistors. Song teaches turning off the light emission control transistors outside the emission period (see the analysis of claim 1, Song discloses that the emission control transistors are configured to turn on to define an emission period. Otherwise, the emission control transistors are turned off outside the emission period). Accordingly, the combination of Park’954 and Song further teaches the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned off . The motivation is the same as the rejection of claim 1. Regarding claim 8 ; Park’954 in view of Song teaches the display device of claim 6 as discussed above. Park’954 further teaches the drive unit simultaneously turns on the initialization transistors provided in all of the plurality of pixels at or after the emission period (Fig.21, para. [0079 and 0087], in the anode initialization period ITINT2, the initialization transistors 1370 are turned on before the emission period. In other words, the initialization transistors are turned off after the emission period of previous frame). Park’954 does not teach turning off the light emission control transistors. Song teaches turning off the light emission control transistors outside the emission period (see the analysis of claim 1, Song discloses that the emission control transistors are configured to turn on to define an emission period. Otherwise, the emission control transistors are turned off outside the emission period). Accordingly, the combination of Park’954 and Song further teaches the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned off . The motivation is the same as the rejection of claim 1. Regarding claim 9 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 further teaches the light emitting element and the initialization transistor are connected to a common power supply (Fig.15, the light emitting diode OLED and the initialization transistor 970 are commonly connected to the second power supply voltage ELVSS). The motivation is the same as the rejection of claim 1. Regarding claim 10 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 further teaches the light emitting element and the drive transistor are provided in series (Fig.20, the light emitting diode OLED and the driving transistor 1330 are connected in series) , and the initialization transistor is provided in parallel with the light emitting element (Fig.15, the initialization transistor 970 and the light emitting diode OLED are connected in parallel). The motivation is the same as the rejection of claim 1. Regarding claim 12 ; Park’954 in view of Song teaches an electronic apparatus (Park’954, Fig.27, para. [0178], an electronic device 1800) comprising a display device, wherein the display device includes a plurality of signal lines extending along a first direction, a plurality of control lines extending along a second direction different from the first direction, a plurality of pixels, and a drive unit that drives the plurality of pixels, each of the plurality of pixels includes a light emitting element, a capacitor, a write transistor that causes a voltage corresponding to a pixel signal supplied from a corresponding signal line among the plurality of signal lines to be accumulated in the capacitor, a drive transistor that supplies a current corresponding to the voltage accumulated in the capacitor to the light emitting element, a light emission control transistor that controls whether or not to supply the current corresponding to the voltage accumulated in the capacitor from the drive transistor to the light emitting element, and an initialization transistor in which one of a source node and a drain node is provided to be connectable to an anode of the light emitting element and the other of the source node and the drain node is provided to be connectable to a cathode of the light emitting element, and the drive unit turns off the initialization transistors provided in all of the plurality of pixels at or before a timing at which the light emission control transistors provided in pixels that simultaneously emit light among the plurality of pixels are turned on (similar to the analysis of claim 1). Regarding claim 13 ; Park’954 in view of Song teaches a driving method of a display device, the display device including a plurality of signal lines extending along a first direction, a plurality of control lines extending along a second direction different from the first direction, a plurality of pixels, and a drive unit that drives the plurality of pixels, each of the plurality of pixels including a light emitting element, a capacitor, a write transistor that causes a voltage corresponding to a pixel signal supplied from a corresponding signal line among the plurality of signal lines to be accumulated in the capacitor, a drive transistor that supplies a current corresponding to the voltage accumulated in the capacitor to the light emitting element, a light emission control transistor that controls whether or not to supply the current corresponding to the voltage accumulated in the capacitor from the drive transistor to the light emitting element, and an initialization transistor in which one of a source node and a drain node is provided to be connectable to an anode of the light emitting element and the other of the source node and the drain node is provided to be connectable to a cathode of the light emitting element, the driving method comprising turning off, by the drive unit, the initialization transistors provided in all of the plurality of pixels at or before a timing at which the light emission control transistors provided in pixels that simultaneously emit light among the plurality of pixels are turned on (similar to the analysis of claim 1) . 07-22-aia AIA Claim s 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Park’954 et al. (US Pub. 2017/0124954 A1, referred to as “Park’954”) in view of Song et al. (US Pub. 2022/0343844 A1) as applied to claim s 1 and 6 above, and further in view of Park et al. (US Pub. 2018/0182287 A1, hereinafter referred to as “Park’287”) . Regarding claim 5 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 in view of Song further teaches the drive unit turns off the initialization transistors provided in all of the plurality of pixels by simultaneous turning off of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels at or before the timing at which the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned on (see the analysis of claim 1 above). Park’954 in view of Song does not teach repeating simultaneous turning off of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels, for each predetermined region defined by the pixels that simultaneously emit light among the plurality of pixels . Park’287 discloses a method of dividing a display panel into a plurality of display blocks; and repeating simultaneously compensating the threshold voltage of driving transistors with respect to all the pixel lines belong to the same display block (Figs.3, 5, and 6; Park’287 discloses a method of dividing a display panel into a plurality of display blocks; simultaneously performing a threshold voltage compensating for all pixels within the same display block; and repeating the threshold voltage compensation for each display block). Accordingly, a combination of Park’954 and Park’287 would render a method of dividing the display panel into a plurality of display blocks, turning off the initialization transistors provided in all of the plurality of pixels within the same display block by simultaneous turning off of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels at or before the timing at which the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned on; and repeating simultaneous turning off of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels, for each display block defined by the pixels that simultaneously emit light among the plurality of pixels. Therefore, Park’954 as modified by Park’287 would teach repeating simultaneous turning off of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels, for each predetermined region defined by the pixels that simultaneously emit light among the plurality of pixels. At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Park’954 in view of Song to include the teaching of Park’287 of dividing a display panel into a plurality of display blocks; and repeating simultaneously compensating the threshold voltage of driving transistors with respect to all the pixel lines belong to the same display block. The motivation would have been in order to improve the display uniformity (e.g., especially in case of a large-size display panel). Regarding claim 7 ; Park’954 in view of Song teaches the display device of claim 6 as discussed above. Park’954 further teaches the drive unit turns on the initialization transistors provided in all of the plurality of pixels at or after the emission period (Fig.21, para. [0079 and 0087], in the anode initialization period ITINT2, the initialization transistors 1370 are turned on before the emission period). Park’954 does not teach turning off the light emission control transistors. Song teaches turning off the light emission control transistors outside the emission period (see the analysis of claim 1, Song discloses that the emission control transistors are configured to turn on to define an emission period. Otherwise, the emission control transistors are turned off outside the emission period). Accordingly, the combination of Park’954 and Song further teaches the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned off . The motivation is the same as the rejection of claim 1. Park’954 in view of Song does not teach repeating simultaneous turning on of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels, for each predetermined region defined by the pixels that simultaneously emit light among the plurality of pixels . Park’287 discloses a method of dividing a display panel into a plurality of display blocks; and repeating simultaneously compensating the threshold voltage of driving transistors with respect to all the pixel lines belong to the same display block (Figs.3, 5, and 6; Park’287 discloses a method of dividing a display panel into a plurality of display blocks; simultaneously performing a threshold voltage compensating for all pixels within the same display block; and repeating the threshold voltage compensation for each display block. Accordingly, a combination of Park’954 and Park’287 would render a method of dividing the display panel into a plurality of display blocks, turning on the initialization transistors provided in all of the plurality of pixels at or after a timing at which the light emission control transistors provided in the pixels that simultaneously emit light among the plurality of pixels are turned off; and repeating simultaneous turning on of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels, for each display block defined by the pixels that simultaneously emit light among the plurality of pixels. Therefore, Park’954 as modified by Park’287 would teach repeating simultaneous turning on of the initialization transistors provided in the pixels that simultaneously emit light among the plurality of pixels, for each predetermined region defined by the pixels that simultaneously emit light among the plurality of pixels. At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Park’954 in view of Song to include the teaching of Park’287 of dividing a display panel into a plurality of display blocks; and repeating simultaneously compensating the threshold voltage of driving transistors with respect to all the pixel lines belong to the same display block. The motivation would have been in order to improve the display uniformity (e.g., especially in case of a large-size display panel) . 07-22-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Park’954 et al. (US Pub. 2017/0124954 A1, referred to as “Park’954”) in view of Song et al. (US Pub. 2022/0343844 A1) as applied to claim 1 above, and further in view of Ono (US Pub. 2013/0169702 A1) . Regarding claim 11 ; Park’954 in view of Song teaches the display device of claim 1 as discussed above. Park’954 in view of Song does not teach the drive unit controls the light emission control transistors provided in all of the plurality of pixels for each predetermined region defined by the pixels that simultaneously emit light among the plurality of pixels . Ono teaches the drive unit (Figs.1 and 3, a scanning/control line driver circuit 14 and a data line drive circuit 15) controls the light emission control transistors provided in all of the plurality of pixels for each predetermined region defined by the pixels that simultaneously emit light among the plurality of pixels (Figs.1 and 3, a display panel is divided into a plurality of odd drive blocks including a plurality of pixels 11A and even drive blocks including a plurality of pixels 11B. In a k th drive block shown at the top stage of FIG. 3, a first control line 131 (k) is connected in common to the gates of the respective switching transistors 116 included in all the pixels 11A in a first drive block. Similarly, a first control line 131 (k+1) is connected in common to the gates of the respective switching transistors 116 included in all the pixels 11B in a second drive block. The first control line 131 has a function of controlling the timing for supplying a drain current of a driver transistor 114 to an organic EL element 113. As such, by applying a control signal to the first control line 131 (k) in the first driver block, transistors 116 of all pixels in the first driver block are simultaneously turned on to emit light. More specifically, Fig.4A, para. [0111], at the time t6, the scanning/control line drive circuit 14 causes the voltage level of the first control line 131 (k) to change from HIGH to LOW. In other words, the respective switching transistors 116 in all of the pixels 11A in the kth drive block are simultaneously turned ON). At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Park’954 in view of Song to include the teaching of Ono of dividing a display panel into a plurality of drive blocks and controlling a plurality of pixels in each driver block to simultaneously emit light. The motivation would have been in order to decrease drive circuit output load and improve display quality (Ono, para. [0018]). Inquiries Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NGUYEN H TRUONG/Examiner, Art Unit 2623 /CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623 Application/Control Number: 19/105,368 Page 2 Art Unit: 2623 Application/Control Number: 19/105,368 Page 3 Art Unit: 2623 Application/Control Number: 19/105,368 Page 4 Art Unit: 2623 Application/Control Number: 19/105,368 Page 5 Art Unit: 2623 Application/Control Number: 19/105,368 Page 6 Art Unit: 2623 Application/Control Number: 19/105,368 Page 7 Art Unit: 2623 Application/Control Number: 19/105,368 Page 8 Art Unit: 2623 Application/Control Number: 19/105,368 Page 9 Art Unit: 2623 Application/Control Number: 19/105,368 Page 10 Art Unit: 2623 Application/Control Number: 19/105,368 Page 11 Art Unit: 2623 Application/Control Number: 19/105,368 Page 12 Art Unit: 2623 Application/Control Number: 19/105,368 Page 13 Art Unit: 2623 Application/Control Number: 19/105,368 Page 14 Art Unit: 2623 Application/Control Number: 19/105,368 Page 15 Art Unit: 2623
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Prosecution Timeline

Feb 21, 2025
Application Filed
Jun 02, 2026
Non-Final Rejection mailed — §103 (current)

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